Pair of bipolar transistor complementary current sources with base current compensation

Abstract

A pair of complementary current sources includes a reference current source, and two complementary current mirrors having the same number of branches provided with bipolar mirror transistors. The bases of the mirror transistors of the complementary mirrors are connected to a common node. One of the complementary mirrors is connected to the reference source. An intermediate current mirror includes a first slave branch connected to the other complementary current mirror, a second slave branch connected to the reference source, and a master branch connected to the output of a trimming circuit for trimming the complementary currents for substantially equalizing the base currents of the mirror transistors of the complementary current mirrors. The input of the trimming circuit is connected to the common node.

That which is claimed is:  
     
       1. A circuit generating complementary currents comprising: 
       a reference current source;  
       first and second complementary current mirrors connected to said reference current source, each current mirror comprising  
       a master branch comprising a bipolar mirror transistor having a base, and  
       at least one slave branch comprising a bipolar mirror transistor having a base connected to the base of said bipolar mirror transistor in the master branch,  
       said first and second complementary current mirrors delivering the complementary currents at the respective slave branches, with said first complementary current mirror being connected to said reference current source via the master branch thereof;  
       an intermediate current mirror comprising a master branch, a first slave branch connected to the master branch of said second complementary current mirrors, and a second slave branch connected to said reference current source; and  
       a trimming circuit for mutually trimming the complementary currents by substantially equalizing base currents of said bipolar mirror transistors of said first and second complementary current mirrors, said trimming circuit being connected between the master branch of said intermediate current mirror and a common node common to the bases of said bipolar mirror transistors of said first and second complementary current mirrors.  
     
     
       2. A circuit according to  claim 1 , wherein a difference between a number of branches of said first and second complementary current mirrors is less than or equal to one so that, when the complementary currents are trimmed, the common node has a sum of currents substantially canceled by said trimming circuit. 
     
     
       3. A circuit according to  claim 1 , wherein said trimming circuit comprises a common-emitter amplifying transistor having a base connected to the common node. 
     
     
       4. A circuit according to  claim 3 , wherein said common-emitter amplifying transistor is of a same type as said bipolar mirror transistors of said second complementary current mirror. 
     
     
       5. A circuit according to  claim 1 , wherein said first complementary current mirror comprises one more slave branch than said second complementary current mirror. 
     
     
       6. A circuit according to  claim 1 , wherein at least one of said first and second complementary current mirrors further comprises an additional transistor, and wherein said bipolar mirror transistor of the master branch therein is diode-connected via said additional transistor, with said bipolar mirror transistor and said additional transistor having a cascode arrangement. 
     
     
       7. A circuit according to  claim 6 , wherein the bases of said bipolar mirror transistors of at least one of said first and second complementary current mirrors are connected to the common node via said additional transistor. 
     
     
       8. A circuit according to  claim 3 , further comprising a voltage down-converter series-connected with an emitter of said transistor of said trimming circuit. 
     
     
       9. A circuit generating complementary currents comprising: 
       a reference current source;  
       first and second complementary current mirrors connected to said reference current source for delivering complementary currents at the respective current mirrors, each current mirror comprising a plurality of mirror transistors;  
       an intermediate current mirror connected to said reference current source and to said second complementary current mirrors; and  
       a trimming circuit for mutually trimming the complementary currents by substantially equalizing control terminal currents of said mirror transistors of said first and second complementary current mirrors, said trimming circuit being connected between said intermediate current mirror and a common node common to the control terminals of said mirror transistors of said first and second complementary current mirrors.  
     
     
       10. A circuit according to  claim 9 , wherein each mirror transistor comprises a bipolar transistor. 
     
     
       11. A circuit according to  claim 9 , wherein each current mirror comprises: 
       a master branch including one of said plurality of mirror transistors; and  
       at least one slave branch including another one of said plurality of mirror transistors, each mirror transistor having a control terminal connected to the control terminal of the other mirror transistor;  
       said first and second complementary current mirrors delivering the complementary currents at the respective slave branches.  
     
     
       12. A circuit according to  claim 9 , wherein said intermediate current mirror comprises a master branch, a first slave branch connected to the master branch of said second complementary current mirror, and a second slave branch connected to said reference current source. 
     
     
       13. A circuit according to  claim 12 , wherein said trimming circuit is connected between the master branch of said intermediate current mirror and the common node. 
     
     
       14. A circuit according to  claim 9 , wherein a difference between a number of branches of said first and second complementary current mirrors is less than or equal to one so that, when the complementary currents are trimmed, the common node has a sum of currents substantially canceled by said trimming circuit. 
     
     
       15. A circuit according to  claim 10 , wherein said first complementary current mirror comprises one more slave branch than said second complementary current mirror. 
     
     
       16. A circuit according to  claim 9 , further comprising a voltage down-converter connected to said trimming circuit. 
     
     
       17. An integrated circuit comprising: 
       first and second pairs of complementary transistors; and  
       a circuit generating complementary currents for biasing said first and second pairs of complementary transistors and comprising  
       a reference current source,  
       first and second complementary current mirrors connected to said reference current source for delivering the complementary currents at the respective current mirrors, each current mirror comprising a plurality of mirror transistors,  
       an intermediate current mirror connected to said reference current source and to said second complementary current mirrors, and  
       a trimming circuit for mutually trimming the complementary currents by substantially equalizing control terminal currents of said mirror transistors of said first and second complementary current mirrors, said trimming circuit being connected between said intermediate current mirror and a common node common to the control terminals of said mirror transistors of said first and second complementary current mirrors.  
     
     
       18. An integrated circuit according to  claim 17 , wherein each mirror transistor and each transistor of said first and second pairs of complementary transistors comprises a bipolar transistor. 
     
     
       19. An integrated circuit according to  claim 17 , wherein each current mirror comprises: 
       a master branch including one of said plurality of mirror transistors; and  
       at least one slave branch including another one of said plurality of mirror transistors, each mirror transistor having a control terminal connected to the control terminal of the other mirror transistor;  
       said first and second complementary current mirrors delivering the complementary currents at the respective slave branches.  
     
     
       20. An integrated circuit according to  claim 17 , wherein said intermediate current mirror comprises a master branch, a first slave branch connected to the master branch of said second complementary current mirror, and a second slave branch connected to said reference current source. 
     
     
       21. An integrated circuit according to  claim 20 , wherein said trimming circuit is connected between the master branch of said intermediate current mirror and the common node. 
     
     
       22. An integrated circuit according to  claim 17 , wherein a difference between a number of branches of said first and second complementary current mirrors is less than or equal to one so that, when the complementary currents are trimmed, the common node has a sum of currents substantially canceled by said trimming circuit. 
     
     
       23. An integrated circuit according to  claim 17 , wherein said trimming circuit comprises a transistor having a control terminal connected to the common node. 
     
     
       24. An integrated circuit according to  claim 17 , further comprising a voltage down-converter connected to said trimming circuit. 
     
     
       25. A method for biasing first and second pairs of complementary transistors using first and second complementary current mirrors connected to a reference current source, and each current mirror comprising a plurality of mirror transistors, the method comprising: 
       delivering complementary currents at the respective current mirrors for the first and second pairs of complementary transistors; and  
       mutually trimming the complementary currents using a trimming circuit by substantially equalizing control terminal currents of the mirror transistors of the first and second complementary current mirrors, the trimming circuit being connected between an intermediate current mirror and a common node common to the control terminals of the mirror transistors of the first and second complementary current mirrors.  
     
     
       26. A method according to  claim 25 , wherein each current mirror comprises a master branch including one of the plurality of mirror transistors; and at least one slave branch including another one of the plurality of mirror transistors, each mirror transistor having a control terminal connected to the control terminal of the other mirror transistor; and wherein the complementary currents are delivered at the respective slave branches of the first and second complementary current mirrors. 
     
     
       27. A method according to  claim 25 , wherein the intermediate current mirror comprises a master branch, a first slave branch connected to the master branch of the second complementary current mirror, and a second slave branch connected to the reference current source. 
     
     
       28. A method according to  claim 25 , wherein a difference between a number of branches of the first and second complementary current mirrors is less than or equal to one so that, when the complementary currents are trimmed, the common node has a sum of currents substantially canceled by the trimming circuit.