Optimized gate implants for reducing dopant effects during gate etching

Abstract

A method and apparatus thereof for fabricating an integrated circuit on a laminate having a gate electrode layer over a silicon dioxide layer. Detection of the gate etch endpoint signal is improved by maximizing the use of a faster etching dopant material (e.g., n-type dopant) and minimizing the use of a slower etching dopant material (e.g., p-type dopant) in the gate electrode layer. In one embodiment, a first portion of the gate electrode layer, substantially corresponding only to the location at which a gate is to be formed, is doped with the slower etching dopant material. The remaining portion of the gate electrode layer is doped with the faster etching dopant material; thus, more of the gate electrode layer is doped with the faster etching dopant material than with the slower etching dopant material. A gate mask is aligned over the gate electrode layer, and the unmasked portions of the gate electrode layer are removed using an etchant. The n-doped portions of gate electrode layer will etch away faster, and because the gate electrode layer is predominantly n-type, a strong and detectable endpoint signal will be induced when the etchant reaches the silicon dioxide layer.

What is claimed is:  
     
       1. A method of fabricating an integrated circuit on a laminate comprising a gate dielectric layer between a gate electrode layer and a substrate, said method comprising the steps of: 
       a) doping a first portion of said gate electrode layer with a first dopant material, said first portion substantially corresponding to a location at which a gate of said integrated circuit is to be formed;  
       b) doping a second portion of said gate electrode layer with a second dopant material, wherein more of said gate electrode layer is doped with said second dopant material than with said first dopant material and wherein said gate electrode layer doped with said second dopant material is etched away at a faster rate than said gate electrode layer doped with said first dopant material;  
       c) applying a gate mask over said gate electrode layer; and  
       d) removing unmasked portions of said gate electrode layer using an etchant, said etchant inducing a detectable endpoint signal upon reaching said gate dielectric layer.  
     
     
       2. The method of fabricating an integrated circuit as recited in  claim 1  wherein said second portion comprises all portions of said gate electrode layer not doped with said first dopant material. 
     
     
       3. The method of fabricating an integrated circuit as recited in  claim 1  wherein said first dopant material is a p-type dopant and said second dopant material is an n-type dopant. 
     
     
       4. The method of fabricating an integrated circuit as recited in  claim 1  wherein said substrate is a semiconductor layer comprised of silicon. 
     
     
       5. The method of fabricating an integrated circuit as recited in  claim 1  wherein said gate electrode layer is comprised of polysilicon. 
     
     
       6. The method of fabricating an integrated circuit as recited in  claim 1  wherein said gate electrode layer is comprised of amorphous silicon. 
     
     
       7. The method of fabricating an integrated circuit as recited in  claim 1  wherein said gate dielectric layer is comprised of silicon dioxide. 
     
     
       8. The method of fabricating an integrated circuit as recited in  claim 1  wherein said integrated circuit is a deep submicron CMOS (complementary metal-oxide semiconductor). 
     
     
       9. A method of fabricating an integrated circuit on a laminate comprising a gate dielectric layer between a gate electrode layer and a substrate, said method comprising the steps of: 
       a) aligning within an alignment tolerance a first implant mask over said gate electrode layer, said first implant mask to allow implantation of a first dopant material into said gate electrode layer at a location at which a first gate of said integrated circuit is to be formed, said first implant mask sized so that said first dopant material does not extend beyond an edge of said first gate plus said alignment tolerance;  
       b) implanting said first dopant material into said gate electrode layer such that said first dopant material does not extend beyond said edge of said first gate plus said alignment tolerance;  
       c) applying a gate mask over said first dopant material; and  
       d) removing said gate electrode layer not under said gate mask using an etchant, said etchant inducing a detectable endpoint signal upon reaching said gate dielectric layer.  
     
     
       10. The method of fabricating an integrated circuit as recited in  claim 9  wherein said step b) comprises: 
       implanting said first dopant material into said gate electrode layer such that said first dopant material does not extend beyond said edge of said first gate.  
     
     
       11. The method of fabricating an integrated circuit as recited in  claim 9  wherein said step b) comprises: 
       implanting said first dopant material into said gate electrode layer such that said first dopant material does not extend to said edge of said first gate.  
     
     
       12. The method of fabricating an integrated circuit as recited in  claim 11  further comprising the step of, prior to said step c): 
       implanting a second dopant material into any portion of said gate electrode layer not implanted with said first dopant material.  
     
     
       13. The method of fabricating an integrated circuit as recited in  claim 12  wherein said first dopant material is a p-type dopant and said second dopant material is an n-type dopant. 
     
     
       14. The method of fabricating an integrated circuit as recited in  claim 12  wherein said first dopant material is an n-type dopant and said second dopant material is a p-type dopant. 
     
     
       15. The method of fabricating an integrated circuit as recited in  claim 9  further comprising the steps of, prior to said step d): 
       a1) aligning within said alignment tolerance a second implant mask over said gate electrode layer, said second implant mask to allow implantation of a second dopant material into said gate electrode layer at a location at which a second gate of said integrated circuit is to be formed, said second implant mask sized so that said second dopant material does not extend beyond an edge of said second gate plus said alignment tolerance;  
       b1) implanting said second dopant material into said gate electrode layer such that said second dopant material does not extend beyond said edge of said second gate plus said alignment tolerance; and  
       c1) applying said gate mask over said second dopant material.  
     
     
       16. The method of fabricating an integrated circuit as recited in  claim 9  wherein said substrate is a semiconductor layer comprised of silicon. 
     
     
       17. The method of fabricating an integrated circuit as recited in  claim 9  wherein said gate electrode layer is comprised of polysilicon. 
     
     
       18. The method of fabricating an integrated circuit as recited in  claim 9  wherein said gate electrode layer is comprised of amorphous silicon. 
     
     
       19. The method of fabricating an integrated circuit as recited in  claim 9  wherein said gate dielectric layer is comprised of silicon dioxide. 
     
     
       20. The method of fabricating an integrated circuit as recited in  claim 9  wherein said integrated circuit is a deep submicron CMOS (complementary metal-oxide semiconductor).