US6542098B1ExpiredUtilityA1

Low-output capacitance, current mode digital-to-analog converter

73
Assignee: INTEL CORPPriority: Sep 26, 2001Filed: Sep 26, 2001Granted: Apr 1, 2003
Est. expirySep 26, 2021(expired)· nominal 20-yr term from priority
H03M 1/742
73
PatentIndex Score
19
Cited by
9
References
7
Claims

Abstract

A low output capacitance, current mode digital-to-analog converter. A low output capacitance is achieved by the use of a current mirror coupled to a plurality of digitally controlled current sources.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A circuit comprising: 
       a set of current sources, wherein each current source in the set of current sources has a port to source current and is digitally controlled by a respective digital control signal belonging to a set of digital control signals;  
       a node connected to the port of each current source in the set of current sources;  
       a current mirror connected to the node; and  
       a sub-circuit connected to the current mirror to provide an analog signal indicative of the set of digital control signals.  
     
     
       2. The circuit as set forth in  claim 1 , wherein the node has a node capacitance and the current mirror has an output capacitance less than the node capacitance. 
     
     
       3. A circuit comprising: 
       a set of current sources, each current source sourcing a current;  
       a node coupled to the set of current sources to source a summed current comprising a sum of the currents sourced by the set of current sources; and  
       a current mirror coupled to the node to source a mirrored current proportional to the summed current, wherein the node has a node capacitance and the current mirror has an output capacitance less than the node capacitance.  
     
     
       4. The circuit as set forth in  claim 3 , wherein each current source is a digitally controlled current source responsive to a digital signal. 
     
     
       5. The circuit as set forth in  claim 4 , further comprising: 
       a sub-circuit coupled to the current mirror to provide a signal responsive to the digital signals.  
     
     
       6. The circuit as set forth in  claim 3 , further comprising: 
       a sub-circuit coupled to the current mirror to provide a signal responsive to the mirrored current.  
     
     
       7. A circuit comprising: 
       a set of current sources, each having a port to source a current;  
       a node connected to the port of each current source in the set of current sources, the node having a node capacitance; and  
       a current mirror connected to the node and having an output capacitance less than the node capacitance.

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