Programmable latch that avoids a non-desired output state

Abstract

A circuit and method are provided for ensuring a non-desired output state of a latch or flip-flop cannot be produced. The latch can be configured as a set dominant, reset dominant, or memory dominant circuit by simply placing programmed voltage values on select transistors of the latch. The programmed values will cause either the set input, the reset input, or both set and reset inputs to have a complimentary effect on the output signals even though the set and reset inputs are at the same logic level. The set, reset, and memory dominant circuit is identical in structure; however, the set, reset, and memory dominant features are derived solely by placing programmed values on corresponding transistors within the identical structure. A generic latch circuit can, therefore, be said to operate in one of three dominant ways depending on the programmed values chosen by a selector and fed to a prioritizer.

What is claimed is:  
     
       1. A latch, comprising: 
       a pair of output conductors;  
       a set conductor and a reset conductor; and  
       a circuit coupled to retain dissimilar logic values upon the pair of output conductors whenever the same logic value is placed on the set and reset conductors, wherein the circuit comprises a selector adapted to selectively place either a power supply voltage, a complementary set voltage, or a complementary reset voltage upon a gate or base conductor of first and second transistors within the circuit.  
     
     
       2. The latch as recited in  claim 1 , wherein the logic value placed on the set conductor is also placed on a first conductor but not a second conductor of the pair of output conductors if the selector places the complementary set voltage upon the first transistor gate or base. 
     
     
       3. The latch as recited in  claim 1 , wherein the logic value placed on the reset conductor is also placed on a second conductor but not a first conductor of the pair of output conductors if the selector places the complementary reset voltage upon the second transistor gate or base. 
     
     
       4. The latch as recited in  claim 1 , wherein the logic value placed on the set conductor and the reset conductor causes no change in logic value on both a first conductor and a second conductor of the pair of output conductors if the selector places the complementary set voltage upon the first transistor gate or base and the complementary reset voltage upon the second transistor gate or base. 
     
     
       5. The latch as recited in  claim 1 , wherein the power supply voltage is either a sourcing power supply or ground. 
     
     
       6. A latch, comprising: 
       a pair of output conductors;  
       a set conductor and a reset conductor; and  
       a circuit coupled to retain dissimilar logic values upon the pair of output conductors whenever the same logic value is placed on the set and reset conductors, wherein the circuit comprises a selector adapted to selectively place either a power supply voltage, a set voltage, or a reset voltage upon a gate or base conductor of first and second transistors within the circuit.  
     
     
       7. The latch as recited in  claim 6 , wherein the logic value placed on the set conductor is also placed on a first conductor but not a second conductor of the pair of output conductors if the selector places the set voltage upon the first transistor gate or base. 
     
     
       8. The latch as recited in  claim 6 , wherein the logic value placed on the reset conductor is also placed on a second conductor but not a first conductor of the pair of output conductors if the selector places the reset voltage upon the second transistor gate or base. 
     
     
       9. The latch as recited in  claim 6 , wherein the logic value placed on the set conductor and the reset conductor causes no change in logic value on both a first conductor and a second conductor of the pair of output conductors if the selector places the set voltage upon the first transistor gate or base and the reset voltage upon the second transistor gate or base. 
     
     
       10. The latch as recited in  claim 6 , wherein the power supply voltage is either a sourcing power supply or ground. 
     
     
       11. A circuit, comprising: 
       a selector adapted to select at least one voltage value from among a set of voltage values forwarded to the selector; and  
       a prioritizer adapted to receive set and reset input signals of the same logic value and latch dissimilar logic values upon output signals depending on which of the at least one voltage value is selected.  
     
     
       12. The circuit as recited in  claim 11 , wherein the selector comprises: 
       selector input conductors coupled to receive the set and reset input signals, or complementary signals thereof; and  
       a selector output conductor coupled to receive either the set input signal, the reset input signal, or both the set and reset input signals, or a signal of opposite logic value to the set input signal, the reset input signal or both the set and reset input signals.  
     
     
       13. The circuit as recited in  claim 12 , wherein the prioritizer comprises: 
       a pair of output conductors;  
       a first transistors and a second transistor, each of which have a gate or base conductor; and  
       wherein one of the pair of output conductors receives the same logic value as the set input signal and the other one of the pair of output conductors receives an opposite logic value as the set input signal whenever the selector output conductor receives the set input signal, or the signal of opposite logic value to the set input signal.  
     
     
       14. The circuit as recited in  claim 12 , wherein the prioritizer comprises: 
       a pair of output conductors;  
       a first transistors and a second transistor, each of which have a gate or base conductor; and  
       wherein one of the pair of output conductors receives the same logic value as the reset input signal and the other one of the pair of output conductors receives an opposite logic value as the reset input signal whenever the selector output conductor receives the reset input signal, or the signal of opposite logic value to the reset input signal.  
     
     
       15. The circuit as recited in  claim 12 , wherein the prioritizer comprises: 
       a pair of output conductors;  
       a first transistors and a second transistor, each of which have a gate or base conductor; and  
       wherein each of the pair of output conductors retains a logic value identical to a logic value previous to when the set and reset input signals are of the same logic value whenever the selector output conductor receives the set input signal and the reset input signal, or the signals of opposite logic value to the set and reset input signals.