Dynamic logic MUX

Abstract

A dynamic logic multiplexer has pull-ups on its input signals that pull-up the input signals when not selected. This reduces leakage current that may contribute to incorrect switching of the output. The output stage of the multiplexer includes a latched dynamic node followed by two gain stages, and an open-drain output.

What is claimed is:  
     
       1. A dynamic multiplexer, comprising: 
       a first dynamic node;  
       a plurality of input structures connected to said first dynamic node;  
       a second dynamic node coupled to said first dynamic node that is responsive to logical voltage level changes on said first dynamic node during an evaluate phase of operation;  
       a first and second gain stage connected in series that are responsive to logical voltage level changes on said second dynamic node;  
       an output transistor controlled by said second gain stage;  
       and wherein said plurality of input structures comprise a precharge FET controlled by a select signal wherein said precharge FET continues to precharge a non-selected data input during said evaluate phase of operation.  
     
     
       2. The dynamic multiplexer of  claim 1  wherein said first dynamic node is a precharge-pulldown node, said second dynamic node is a precharge-pullup node, and said precharge FET is a PFET. 
     
     
       3. The dynamic multiplexer of  claim 1  wherein said first dynamic node is a precharge-pullup node, said second dynamic node is a precharge pulldown node, and said precharge FET is a NFET. 
     
     
       4. The dynamic multiplexer of  claim 1 , comprising: 
       a node holder connected to said second dynamic node.  
     
     
       5. The dynamic multiplexer of  claim 4  wherein said node holder comprises said first gain stage. 
     
     
       6. A multiplexer, comprising: 
       an input structure that precharges its data input during an evaluate phase when said input structure is not selected and during a precharge phase;  
       a first dynamic node connected to a plurality of said input structures;  
       a first gain stage having a first gain input coupled to said first dynamic node and a first gain output;  
       a second gain stage having a second gain input connected to said first gain output;  
       an output transistor connected to a second gain stage output.  
     
     
       7. The multiplexer of  claim 6  wherein said first gain stage is part of a node holder. 
     
     
       8. The multiplexer of  claim 6  wherein said first dynamic node is a precharge-pulldown node and said plurality of input structures precharge said data input to a logical high voltage level. 
     
     
       9. A multiplexer, comprising: 
       a plurality of input structures wherein said input structures comprise a first switching device of a first type and a second switching device of a second type and said first switching device precharges a data input when a control signal is in a first logical state and said second switching device connects a data input of said input structure to a first dynamic node when said control signal is in a second logical state;  
       a first gain stage having a first input and a first output, said first input coupled to said first dynamic node;  
       a second gain stage having a second input coupled to said first output and a second output; and,  
       an output transistor being controlled by said second output.  
     
     
       10. The multiplexer of  claim 9 , comprising a second dynamic node coupled between said first dynamic node and said first input. 
     
     
       11. The multiplexer of  claim 9  wherein said first switching device of a first type is a PFET. 
     
     
       12. The multiplexer of  claim 9  wherein said second switching device of a second type is a NFET. 
     
     
       13. The multiplexer of  claim 9  wherein said first switching device of a first type is a NFET. 
     
     
       14. The multiplexer of  claim 9  wherein said second switching device of a second type is a PFET. 
     
     
       15. The multiplexer of  claim 9  wherein said first switching device of a first type is a PFET and said second switching device of a second type is a NFET. 
     
     
       16. The multiplexer of  claim 9  wherein said first switching device of a first type is a NFET and said second switching device of a second type is a PFET. 
     
     
       17. The multiplexer of  claim 15  wherein said first dynamic node is a precharge-pulldown node. 
     
     
       18. The multiplexer of  claim 16  wherein said first dynamic node is a precharge-pullup node. 
     
     
       19. The multiplexer of  claim 9  wherein said first gain stage is part of a node holder. 
     
     
       20. The multiplexer of  claim 19  wherein said first switching device of a first type is a NFET and said second switching device of a second type is a PFET and said first dynamic node is a precharge-pulldown node.