Clock recovery and detection of rapid phase transients

Abstract

Systems and methods are described for clock recovery and detection of rapid phase transients. An apparatus includes: a numerically controlled oscillator; a phase detector coupled to the numerically controlled oscillator; and a multiplexer coupled to the phase detector and the numerically controlled oscillator, wherein a) the phase detector sets a state variable indicator to either i) a high value if an output phase of the numerically controlled oscillator lags an incoming signal phase, or ii) a low value if the output phase leads the incoming signal phase, b) the multiplexer sends either i) a high increment to the numerically controlled oscillator if the state variable indicator has been set to the high value, or ii) a low increment to the numerically controlled oscillator if the state variable indicator has been set to the low value, and c) the numerically controlled oscillator either i) advances the output phase if the high increment has been sent to the numerically controlled oscillator, or ii) retards the output phase if the low increment has been sent to the numerically controlled oscillator. A method includes incrementing a high counter once every clock cycle if a state variable indicator is high; clearing a low counter if the state variable indicator is high; incrementing the low counter once every clock cycle if the state variable indicator is low; clearing the high counter if the state variable indicator is low; and triggering an alarm signal if either i) the low counter exceeds a low count threshold or ii) the high counter exceeds a high count threshold.

What is claimed is:  
     
       1. A method, comprising: 
       incrementing a high counter once every clock cycle when a state variable indicator is high;  
       clearing a low counter when the state variable indicator is high;  
       incrementing the low counter once every clock cycle when the state variable indicator is low;  
       clearing the high counter when the state variable indicator is low; and  
       triggering an alarm signal when either  
       i) the low counter exceeds a low count threshold or  
       ii) the high counter exceeds a high count threshold.  
     
     
       2. The method of  claim 1 , wherein the state variable indicator is a binary modulo indicator DWN+/UP. 
     
     
       3. The method of  claim 1 , further comprising, when the alarm signal is triggered, temporarily disabling a local oscillator discipline arrangement. 
     
     
       4. The method of  claim 1 , further comprising: 
       setting the state variable indicator to either  
       i) a high value when an output phase of a numerically controlled oscillator lags an incoming signal phase, or  
       ii) a low value when the output phase leads the incoming signal phase; then  
       sending either  
       i) a high increment to the numerically controlled oscillator when the state variable indicator has been set to the high value, or  
       ii) a low increment to the numerically controlled oscillator when the state variable indicator has been set to the low value; and then either  
       i) advancing the output phase when the high increment has been sent to the numerically controlled oscillator, or  
       ii) retarding the output phase when the low increment has been sent to the numerically controlled oscillator.  
     
     
       5. A computer program, comprising computer or machine readable program elements translatable for implementing the method of  claim 1 . 
     
     
       6. An apparatus for performing the method of  claim 1 . 
     
     
       7. A method of detection of a rapid change in an incoming T 1  signal, comprising the method of  claim 1 . 
     
     
       8. An apparatus, comprising: 
       a source of a clock signal;  
       a source of a state variable indicator;  
       a high counter coupled to the source of the clock signal and the source of a state variable indicator, the high counter incremented once every clock cycle when the state variable indicator is high;  
       a low counter coupled to the source of the clock signal and the source of the state variable indicator, the low counter incremented once every clock cycle when the state variable indicator is low; and  
       an alarm coupled to the high counter and the low counter, the alarm triggered when either  
       i) the low counter exceeds a low count threshold or  
       ii) the high counter exceeds a high count threshold,  
       wherein the high counter is cleared when the state variable indicator is low, and the low counter is cleared when the state variable indicator is high. 
     
     
       9. The apparatus of  claim 8 , wherein said source of a clock signal is an incoming clock signal SIG-T 1 . 
     
     
       10. The apparatus of  claim 8 , further comprising a local oscillator discipline arrangement coupled to the alarm. 
     
     
       11. A method of detecting a rapid change in an incoming T 1  signal, comprising deploying the apparatus of  claim 8 . 
     
     
       12. An integrated circuit, comprising the apparatus of  claim 8 . 
     
     
       13. A circuit board, comprising the integrated circuit of  claim 12 . 
     
     
       14. A computer, comprising the circuit board of  claim 13 . 
     
     
       15. A network, comprising the computer of  claim 14 . 
     
     
       16. A kit, comprising: 
       a source of a clock signal;  
       a source of a state variable indicator;  
       a high counter coupled to the source of the clock signal and the source of a state variable indicator, the high counter incremented once every clock cycle when the state variable indicator is high;  
       a low counter coupled to the source of the clock signal and the source of the state variable indicator, the low counter incremented once every clock cycle when the state variable indicator is low; and  
       an alarm coupled to the high counter and the low counter, the alarm triggered when either  
       i) the low counter exceeds a low count threshold or  
       ii) the high counter exceeds a high count threshold,  
       wherein the high counter is cleared when the state variable indicator is low, and the low counter is cleared when the state variable indicator is high.