Non-volatile memory and fabrication thereof

Abstract

A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a substrate having a trench therein, a buried bit-line in the substrate crossing the trench, a word-line covering at least the trench and crossing over the buried bit-line, and a charge trapping layer between the substrate and the word-line.

What is claimed is:  
     
       1. A non-volatile memory, comprising: 
       a substrate having a trench therein;  
       a buried bit-line in the substrate crossing the trench;  
       a word-line covering at least the trench and crossing over the buried bit-line; and  
       a charge trapping layer between the substrate and the word-line.  
     
     
       2. The non-volatile memory of  claim 1 , wherein the trench comprises a U-shaped trench. 
     
     
       3. The non-volatile memory of  claim 1 , wherein the charge trapping layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) layer. 
     
     
       4. The non-volatile memory of  claim 1 , further comprising a buried bit-line oxide layer between the buried bit-line and the word-line. 
     
     
       5. The non-volatile memory of  claim 1 , wherein the word-line comprises polysilicon. 
     
     
       6. A method for fabricating a non-volatile memory, comprising the steps of: 
       providing a substrate;  
       forming a trench in the substrate;  
       forming a charge trapping layer on the substrate and on the trench;  
       exposing a strip region of the substrate that crosses the trench;  
       forming a buried bit-line in the substrate within the strip region;  
       forming a buried bit-line oxide layer on the buried bit-line; and  
       forming a word-line over the substrate, the word line covering the trench and crossing over the buried bit-line.  
     
     
       7. The method of  claim 6 , wherein the trench comprises a U-shaped trench. 
     
     
       8. The method of  claim 7 , wherein the method for forming the trench comprises anisotropic etching. 
     
     
       9. The method of  claim 6 , wherein the charge trapping layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) layer. 
     
     
       10. The method of  claim 9 , wherein forming the ONO layer on the substrate comprises: 
       forming a first silicon oxide layer on the substrate by thermal oxidation;  
       forming a silicon nitride layer on the first silicon oxide layer by low pressure chemical vapor deposition (LPCVD); and  
       forming a second silicon oxide layer on the silicon nitride layer by thermal oxidation.  
     
     
       11. The method of  claim 6 , wherein the method for forming the buried bit-line comprises ion implantation. 
     
     
       12. The method of  claim 6 , wherein the word-line comprises polysilicon.