US6559700B2ExpiredUtilityA1

Semiconductor integrated circuit

31
Assignee: SHARP KKPriority: Nov 7, 2000Filed: Nov 7, 2001Granted: May 6, 2003
Est. expiryNov 7, 2020(expired)· nominal 20-yr term from priority
Inventors:Masashi Yonemaru
H03K 19/1737H03K 19/0013H03K 19/01721
31
PatentIndex Score
0
Cited by
8
References
29
Claims

Abstract

A semiconductor integrated circuit includes a plurality of logical elements connected in series or parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and a buffer circuit connected between a logical element group including at least two of the plurality of logical elements and another logical element group including at least two of the plurality of logical elements.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A semiconductor integrated circuit, comprising: 
       a plurality of logical elements connected in series, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and  
       a buffer circuit connected directly between a first logical element group including at least three of the plurality of logical elements and a second logical element group including at least two of the plurality of logical elements,  
       wherein an input terminal is connected to said first logical element group and an output voltage of said first logical element group is wave-form shaped by the buffer circuit so that the buffer circuit provides an output voltage having a steep transit characteristic to the second logical element group.  
     
     
       2. The semiconductor integrated circuit according to  claim 1 , wherein the logical elements are N-type MOSFETs. 
     
     
       3. The semiconductor integrated circuit according to  claim 1 , wherein the logical elements are P-type MOSFETs. 
     
     
       4. The semiconductor integrated circuit according to  claim 1 , wherein the buffer circuit is a CMOS inverter including a P-type MOSFET and an N-type MOSFET. 
     
     
       5. The semiconductor integrated circuit according to  claim 1 , wherein the buffer circuit includes a first P-type MOSFET and a CMOS inverter including a second P-type MOSFET and an N-type MOSFET, a source of the first P-type MOSFET is connected to a power supply line, and a drain and a gate of the first P-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter. 
     
     
       6. The semiconductor integrated circuit according to  claim 1 , wherein the buffer circuit includes a first N-type MOSFET and a CMOS inverter including a P-type MOSFET and a second N-type MOSFET, a source of the first N-type MOSFET is connected to a ground line, and a drain and a gate of the first N-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter. 
     
     
       7. The semiconductor integrated circuit according to  claim 4 , wherein a threshold voltage of the P-type MOSFET is set to be a high level. 
     
     
       8. The semiconductor integrated circuit according to  claim 5 , wherein a threshold voltage of the second P-type MOSFET is set to be a high level. 
     
     
       9. The semiconductor integrated circuit according to  claim 4 , wherein a threshold voltage of the N-type MOSFET is set to be a high level. 
     
     
       10. The semiconductor integrated circuit according to  claim 6 , wherein a threshold voltage of the second N-type MOSFET is set to be a high level. 
     
     
       11. The semiconductor integrated circuit according to  claim 1 , wherein the buffer circuit is a non-inverter type buffer circuit including two inverter circuits connected in series. 
     
     
       12. The semiconductor integrated circuit according to  claim 11 , wherein one of the inverter circuits of the non-inverter type buffer circuit is a buffer circuit including a CMOS inverter including a P-type MOSFET and an N-type MOSFET. 
     
     
       13. The semiconductor integrated circuit according to  claim 11 , wherein one of the inverter circuits of the non-inverter type buffer circuit is a buffer circuit including a first P-type MOSFET and a CMOS inverter including a second P-type MOSFET and an N-type MOSFET, a source of the first P-type MOSFET is connected to a power supply line, and a drain and a gate of the first P-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter. 
     
     
       14. The semiconductor integrated circuit according to  claim 11 , wherein one of the inverter circuits of the non-inverter type buffer circuit is a buffer circuit including a first N-type MOSFET and a CMOS inverter including a P-type MOSFET and a second N-type MOSFET, a source of the first N-type MOSFET is connected to a ground line, and a drain and a gate of the first N-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter. 
     
     
       15. A semiconductor integrated circuit, comprising: 
       a plurality of logical elements connected in parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate;  
       a buffer circuit connected directly between a first logical element group and a second logical element group, the first logical element group including at least two logical elements connected in parallel in series with another two logical elements connected in parallel in series with yet another two logical elements connected in parallel, the second logical element group including at least two logical elements connected in parallel in series with another two logical elements connected in parallel, wherein  
       an input terminal is connected to said first logical element group and an output voltage of said first logical element group is wave-form shaped by the buffer circuit so that the buffer circuit provides an output voltage having a steep transit characteristic to the second logical element group.  
     
     
       16. The semiconductor integrated circuit according to  claim 15 , wherein the logical elements are CMOS transmission gates each including a P-type MOSFET and an N-type MOSFET. 
     
     
       17. The semiconductor integrated circuit according to  claim 15 , wherein the buffer circuit is a CMOS inverter including a P-type MOSFET and an N-type MOSFET. 
     
     
       18. The semiconductor integrated circuit according to  claim 15 , herein the buffer circuit includes a first P-type MOSFET and a CMOS inverter including a second P-type MOSFET and an N-type MOSFET, a source of the first P-type MOSFET is connected to a power supply line, and a drain and a gate of the first P-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter. 
     
     
       19. The semiconductor integrated circuit according to  claim 15 , wherein the buffer circuit includes a first N-type MOSFET and a CMOS inverter including a P-type MOSFET and a second N-type MOSFET, a source of the first N-type MOSFET is connected to a ground line, and a drain and a gate of the first N-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter. 
     
     
       20. The semiconductor integrated circuit according to  claim 17 , herein a threshold voltage of the P-type MOSFET is set to be a high level. 
     
     
       21. The semiconductor integrated circuit according to  claim 18 , wherein a threshold voltage of the second P-type MOSFET is set to be a high level. 
     
     
       22. The semiconductor integrated circuit according to  claim 17 , wherein a threshold voltage of the N-type MOSFET is set to be a high level. 
     
     
       23. The semiconductor integrated circuit according to  claim 19 , wherein a threshold voltage of the second N-type MOSFET is set to be a high level. 
     
     
       24. The semiconductor integrated circuit according to  claim 15 , wherein the buffer circuit is a non-inverter type buffer circuit including two inverter circuits connected in series. 
     
     
       25. The semiconductor integrated circuit according to  claim 24 , wherein one of the inverter circuits of the non-inverter type buffer circuit is a buffer circuit including a CMOS inverter including a P-type MOSFET and an N-type MOSFET. 
     
     
       26. The semiconductor integrated circuit according to  claim 24 , wherein one of the inverter circuits of the non-inverter type buffer circuit is a buffer circuit including a first P-type MOSFET and a CMOS inverter including a second P-type MOSFET and an N-type MOSFET, a source of the first P-type MOSFET is connected to a power supply line, and a drain and a gate of the first P-type MOSFET are respectfully connected to an input terminal and an output terminal of the CMOS inverter. 
     
     
       27. The semiconductor integrated circuit according to  claim 24 , herein one of the inverter circuits of the non-inverter type buffer circuit is a buffer circuit including a first N-type MOSFET and a CMOS inverter including a P-type MOSFET and a second N-type MOSFET, a source of the first N-type MOSFET is connected to a ground line, and a drain and a gate of the first N-type MOSFET are respectfully connected to an input terminal and an output terminal of the CMOS inverter. 
     
     
       28. A semiconductor integrated circuit, comprising: 
       a plurality of logical elements connected in a series, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and  
       a buffer circuit connected directly between a first logical element group including at least three of the plurality of logical elements and a second logical element group including at least two of the plurality of logical elements, wherein  
       an input terminal is connected to said first logical element group and an output voltage of said first logical element group is wave-form shaped by the buffer circuit so that the buffer circuit provides an output voltage having a steep transit characteristic to the second logical element group;  
       and wherein the semiconductor integrated circuit is formed on an SOI substrate.  
     
     
       29. A semiconductor integrated circuit, comprising: 
       a plurality of logical elements connected in parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and  
       a buffer circuit connected directly between a first logical element group and a second logical element group, the first logical element group including at least two logical elements connected in parallel in series with another two logical elements connected in parallel in series with yet another two logical elements connected in parallel, the second logical element group including at least two logical elements connected in parallel in series with another two logical elements connected in parallel, wherein  
       an input terminal is connected to said first logical element group and an output voltage of said first logical element group is wave-form shaped by the buffer circuit so that the buffer circuit provides an output voltage having a steep transit characteristic to the second logical element group; and  
       wherein the semiconductor integrated circuit is formed on an SOI substrate.

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