Method for forming a storage node of a capacitor

Abstract

A method for forming the storage node of a capacitor which simplifies its process, and improves the electrical characteristics of semiconductor products by forming the storage node of a capacitor with no stepped portion between cell regions and peripheral circuit regions necessary for memory storage of semiconductor products of the next generation to which a fine line width is applied, and, at the same time, forming a guard ring for dividing the cell regions and the peripheral circuit regions.

What is claimed:  
     
       1. A method for forming the storage node of a capacitor, comprising: 
       forming a gate having a bit line and a spacer in a cell region of on a semiconductor substrate, the semiconductor substrate also having a peripheral circuit region;  
       depositing a first inter-layer insulating film, a barrier nitride film and a second inter-layer insulating film on the gate and the substrate;  
       forming a contact hole by depositing a contact mask on the inter-layer insulating film and the barrier nitride film and etching them, and then forming a polysilicon plug by depositing a doped polysilicon in the contact hole and planarizing the same by a polishing process;  
       depositing a capacitor oxide film and a hard mask polysilicon film on the resultant material;  
       forming an antireflection film on the hard mask polysilicon film and thereafter stacking a photoresist film thereon;  
       forming a contact in the cell region and a guard ring for dividing the cell region and the peripheral circuit region by firstly etching the hard mask polysilicon film using the photoresist film as a mask and secondly etching the capacitor oxide film so that the polysilicon plug is exposed to the etched hard mask polysilicon film;  
       forming a doped polysilicon layer and hemispherical grain protrusions in the contact and guard ring;  
       stacking a buried layer on the doped polysilicon layer and hemispherical grain protrusions in the contact and guard ring and thereafter planarizing the same with a CMP process;  
       stacking a photoresist film on top of the doped polysilicon layer and hemispherical grain protrusions disposed in the guard ring in the peripheral circuit region and thereafter removing the buried layer buried disposed in the contact in the cell region; and  
       forming a storage node by removing the capacitor oxide film stacked in the cell region and the buried layer and the grain protrusions by using the photoresist film as a mask.  
     
     
       2. The method according to  claim 1 , wherein the barrier nitride film is formed with a thickness ranging from about 200 to about 1500 Å by a LP-CVD method or a PE-CVD method. 
     
     
       3. The method according to  claim 1 , wherein, when the barrier nitride film and the first and second inter-layer insulating films are dry etched, they are over-etched at about 30% of the thickness thereof. 
     
     
       4. The method according to  claim 1 , wherein, upon forming a polysilicon plug in the contact hole, doped polysilicon having a phosphorus concentration of more than 4×10 20  atoms/sec is used by a LP-CVD method or a RTP method. 
     
     
       5. The method according to  claim 1 , wherein the capacitor oxide film is formed by depositing a PE-TEOS film or a USG film at a thickness at which a capacitance of 25 fF/cell can be obtained. 
     
     
       6. The method according to  claim 1 , wherein the antireflection film is formed by stacking a non-organic or an organic substance at a thickness ranging from about 100 to about 1000 Å. 
     
     
       7. The method according to  claim 1 , wherein, upon etching the capacitor film, the barrier nitride film at a lower portion thereof is used as an etching barrier, and is over-etched from about 10 to about 100% of the thickness thereof. 
     
     
       8. The method according to  claim 1 , wherein the guard ring is formed to with a width to 0.1 to about 0.5 μm. 
     
     
       9. The method according to  claim 1 , wherein an etching selection ratio of the capacitor oxide film to the barrier nitride film ranges from about 5:1 to about 20:1. 
     
     
       10. The method according to  claim 1 , wherein the grain protrusions of the storage node is thermal doped or plasma doped under a phosphorus gaseous atmosphere. 
     
     
       11. The method according to  claim 1 , wherein the thickness of the storage node is formed less than about 1000 Å to prevent short in a cylindrical cylinder. 
     
     
       12. The method according to  claim 1 , wherein the buried layer is stacked at a thickness ranging from about 0.1 to about 0.5 μm, and the photoresist film is stacked at a thickness ranging from about 0.1 to about 0.5 μm. 
     
     
       13. The method according to  claim 1 , wherein, upon performing the CMP process after stacking the buried layer inside the polysilicon grain protrusions, the storage node and the hard mask polysilicon film are CMP polished at about 1 to about 20% of the thickness thereof. 
     
     
       14. The method according to  claim 1 , wherein, upon removing the capacitor oxide film by etching, it is over-etched at about 50 to about 500% of the thickness thereof by using the barrier nitride film as an etching barrier film. 
     
     
       15. A method for forming the storage node of a capacitor, comprising the steps of: 
       forming a gate having a bit line and a spacer on a semiconductor substrate;  
       stacking a polysilicon layer on the gate and substrate thereafter forming a polysilicon plug adjacent the gate by a CMP process;  
       depositing an inter-layer insulating film and a barrier nitride film on the gate and plug;  
       depositing a capacitor oxide film and a hard mask polysilicon film on the barrier nitride film;  
       forming an antireflection film on the hard mask polysilicon film to thereafter stack a photoresist film thereon; and  
       opening the polysilicon plug by firstly etching the hard mask polysilicon film using the photoresist film as a mask and then etching the barrier nitride film and the inter-layer insulating film.  
     
     
       16. The method according to  claim 15 , wherein the inter-layer insulating film is stacked at a thickness of less than about 3000 Å. 
     
     
       17. The method according to  claim 15 , wherein the barrier nitride film is formed at a thickness ranging from about 200 to about 1500 Å by a LP-CVD method or a PE-CVD method.