Hetero-interface avalance photodetector

Abstract

An avalanche photodetector (APD) is made from composite semiconductor materials. The absorption region of the APD is formed in a n-type InGaAs layer. The multiplication region of the APD is formed in a p-type silicon layer. The two layers are bonded together. The p-type silicon layer may be supported on an n+ type silicon substrate. A p-n junction formed at the interface between the silicon layer and the substrate. Alternatively, the n-type InGaAs layer may be supported on an InP substrate. In this case, a p-n junction is formed by making n-doped surface regions in the p-type silicon superlayer. In either case, the p-n junction is reverse biased for avalanche multiplication of charge carriers. The maximum of the electric field distribution in the APD under reverse bias operating conditions is located at p-n junction. This maximum is at a distance equal to about the thickness of the p-type silicon layer away from the absorption region. The electric field values in the absorption region depend primarily on the thickness and doping level of the p-type silicon layer. The electric field values in the absorption region are controllably set for obtaining high carrier velocities in the absorption region without causing carrier tunneling.

What is claimed is:  
     
       1. A photodetector comprising: 
       an absorption region made from a first semiconductor material, said absorption region configured to photogenerate charge carriers in response to incident light;  
       a multiplication region made from a second semiconductor material configured to receive at least a fraction of said photogenerated charge carriers, and comprising a p-n junction to substantially multiply the number of charge carriers by avalanche multiplication; and  
       contacts for applying a reverse bias voltage across said photodetector,  
       wherein said semiconductor materials have lattice constants which differ from each other by more than 1%, and said p-n junction is at a distance of more than about two tenths of a micron from said absorption region.  
     
     
       2. A photodetector comprising: 
       an absorption region made from a first semiconductor material, said absorption region configured to photogenerate charge carriers in response to incident light;  
       a multiplication region made from a second semiconductor material configured to receive at least a fraction of said photogenerated charge carriers, and comprising a p-n junction to substantially multiply the number of charge carriers by avalanche multiplication, said p-n junction having an unbiased depletion width; and  
       contacts for applying a reverse bias voltage across said photodetector,  
       wherein said regions are in physical proximity, said semiconductor materials have lattice constants which differ from each other by more than 1%, and wherein said p-n junction is at a distance greater than said unbiased depletion width away from said absorption region.  
     
     
       3. The photodetector of  claim 2  wherein said first semiconductor material is a compound semiconductor layer disposed on a substrate wafer, and wherein said second semiconductor material is a Group IV semiconductor layer disposed on top of said compound semiconductor layer. 
     
     
       4. The photodetector of  claim 3  wherein said first semiconductor material is an InGaAs layer epitaxially grown on an InP substrate and said second semiconductor material is a thin silicon layer. 
     
     
       5. A monolithic circuit comprising: 
       the photodetector of  claim 3 ; and  
       components at least partially formed in said compound semiconductor layer adjoining said photodetector.  
     
     
       6. The photodetector of  claim 3  wherein an active device area is defined by forming a mesa through said through said Group IV semiconductor layer and said compound semiconductor layer. 
     
     
       7. The photodetector of  claim 2  wherein said second semiconductor material is a Group IV semiconductor layer disposed on a substrate wafer, and said first semiconductor material is a compound semiconductor layer disposed on said Group IV semiconductor layer. 
     
     
       8. The photodetector of  claim 7  wherein an active device area is defined by forming a mesa through said through said Group IV semiconductor layer and said compound semiconductor layer. 
     
     
       9. A photodetector comprising: 
       an absorption region made from a first semiconductor material, said absorption region configured to photogenerate charge carriers in response to incident light;  
       a multiplication region made from a second semiconductor material configured to receive at least a fraction of said photogenerated charge carriers, said multiplication region comprising a p-n junction to substantially multiply the number of charge carriers by avalanche multiplication, and  
       contacts for applying a reverse bias voltage across said photodetector,  
       wherein said semiconductor materials have lattice constants which differ from each other by more than 1% and the region of lowest doping of the p-n junction is adjacent to the absorption region, such that an electric field maximum for said applied reverse bias voltage is located in said multiplication region a substantial distance away from said absorption region, and as said reverse bias voltage increases electric fields in said photodetector increase and move toward said absorption region.  
     
     
       10. The photodetector of  claim 9  wherein said second semiconductor material is an epitaxially-grown layer. 
     
     
       11. The photodetector of  claim 9  wherein said second semiconductor material is a thinned semiconductor layer. 
     
     
       12. The photodetector of  claim 9  wherein by dopant concentration and said thickness are selected so that at an operating reverse bias voltage said electric field in said absorption region has a value corresponding to about the maximum carrier velocities in said first semiconductor material, said value below electric field values which cause carrier tunneling in said first semiconductor material. 
     
     
       13. A photodetector comprising: 
       an n +  type silicon substrate;  
       a p −  type epitaxial silicon layer grown on said n +  type silicon substrate;  
       a n-type InGaAs absorption layer bonded to said p− type epitaxial silicon layer;  
       a first contact formed on said n +  type silicon substrate; and  
       a second contact formed on said n-type InGaAs absorption layer,  
       wherein in operation of said photodetector a reverse bias voltage is applied across said contacts causing an electric field maximum at about the interface between said n +  type silicon substrate and said p− type epitaxial silicon layer.  
     
     
       14. The photodetector of  claim 13  wherein said n +  type silicon substrate comprises a substrate having a resistivity between about 10 to 30 Mohm-cm, wherein said n-type InGaAs absorption layer is about 1000 nm thick and has an unintentional doping level less than about 1×10 15  atoms/cm −3) , and wherein said p− type epitaxial silicon layer is about 1 um thick and has a doping level of about 3×10 16  atoms/cm .−3 . 
     
     
       15. The photodetector of  claim 13  wherein said first contact comprises an n implant layer. 
     
     
       16. The photodetector of  claim 13  wherein said first contact comprises an n +  implant layer.