Non-volatile multi-level semiconductor flash memory device and method of driving same

Abstract

In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

What is claimed is:  
     
       1. A nonvolatile memory comprising: 
       a plurality of word lines;  
       a plurality of memory cells; and  
       a control circuit,  
       wherein each of said word lines connects to corresponding ones of said memory cells,  
       wherein each of said memory cells is capable of storing multi-bit data including a first bit data and a second bit data,  
       wherein said control circuit controls a read operation corresponding to a read command with an address received from outside of the nonvolatile memory,  
       wherein said control circuit controls to select one of said word lines and to read said first bit data from said memory cells connected to said selected word line, when receiving said read command with a first type address, and  
       wherein said control circuit controls to select said selected word line and to read said second bit data from said memory cells, when receiving said read command with a second type address.  
     
     
       2. A nonvolatile memory according to  claim 1 , 
       wherein said received address includes information for deciding whether said address type is said first type address or said second type address, and  
       wherein said control circuit decides said address type using said information.  
     
     
       3. A nonvolatile memory according to  claim 2 , 
       wherein said control circuit selects said selected word line using said received address except said information.  
     
     
       4. A nonvolatile memory according to  claim 3 , 
       wherein said information Is one bit length, and  
       wherein, when said information is a first state, then said received address is said first type address, and, when said information is a second state, then said received address is said second type address.  
     
     
       5. A nonvolatile memory according to  claim 1 , 
       wherein in said read operation, said control circuit controls to supply a read voltage to said selected word line, and  
       wherein a voltage level of said read voltage for reading said first bit data is different from a voltage level for reading said second bit data.  
     
     
       6. A nonvolatile memory according to  claim 5 , 
       wherein said control circuit controls to supply said read voltage at one time when reading said first bit data, and  
       wherein said control circuit controls to supply said read voltage at one or more times when reading said second bit data.  
     
     
       7. A nonvolatile memory according to  claim 6 , 
       wherein said voltage level of said read voltage for reading said first bit data is intermediate said voltage levels for reading said second bit data at a first time and at a second time.  
     
     
       8. A nonvolatile memory according to  claim 1 , 
       wherein a time period for reading said first bit data is equal to or shorter than a time period for reading said second bit data.