Vernier structures that substantially eliminate offset signals

Abstract

Verniers are provided that substantially eliminate DC offset signals as they convert a differential input signal S in to a differential output signal S out with a conversion gain that corresponds to a digital command signal. The verniers are especially suited for use with multiplying digital-to-analog converters (MDACs) in communication systems. An exemplary use is forming line drivers to drive load impedances (e.g., coaxial cables).

We claim:  
     
       1. A vernier that converts a differential input signal to a differential output current with a conversion gain that corresponds to a digital command signal, comprising: 
       first, second and third current sources that respectively provide first, second and third currents.  
       an input differential pair of first and second input transistors arranged to steer said third current along first and second current paths in response to said differential input signal;  
       first and second reference transistors that have first and second reference device sizes and that respectively couple said first current path to said first current source and couple said second current path to said second current source; and  
       at least one pair of first and second subtraction transistors that have first and second subtraction device sizes that are less than said first and second reference device sizes and that, in response to said digital command signal, respectively couple said first current path to said second current source and couple said second current path to said first current source;  
       wherein said differential output current is generated by differences between said first and second currents and those portions of said third current that are directed towards or away from said first and second current sources.  
     
     
       2. The vernier of  claim 1 , wherein said third current substantially equals the sum of said first and second currents. 
     
     
       3. The vernier of  claim 2 , wherein said first and second currents are substantially equal. 
     
     
       4. The vernier of  claim 1 , wherein said first and second reference transistors and said first and second subtraction transistors are biased by a common reference signal. 
     
     
       5. The vernier of  claim 1 , wherein said first and second reference device sizes are substantially equal and said first and second subtraction device sizes are substantially equal. 
     
     
       6. The vernier of  claim 1 , wherein all first and second subtraction transistors have substantially equal subtraction device sizes. 
     
     
       7. The vernier of  claim 1 , wherein one pair of first and second subtraction transistors have subtraction device sizes that differ from the subtraction device sizes of another pair of first and second subtraction transistors. 
     
     
       8. The vernier of  claim 1 , further including, for each pair of first and second subtraction transistors, first and second switches that are inserted in series with a terminal of said first and second subtraction transistors respectively wherein said first and second switches respond to a respective bit of said digital command signal. 
     
     
       9. The vernier of  claim 1 , further including at least one trim transistor that is selectively coupled in parallel with one of said first and second reference transistors to adjust said differential output current. 
     
     
       10. The vernier of  claim 1 , wherein said first and second input transistors, said first and second reference transistors and said first and second subtraction transistors are metal-oxide-semiconductor transistors. 
     
     
       11. The vernier of  claim 1 , wherein said first and second input transistors, said first and second reference transistors and said first and second subtraction transistors are bipolar junction transistors. 
     
     
       12. A vernier that converts a differential input signal at first and second sides of an input port to a differential output current with a conversion gain that corresponds to a digital command signal, comprising: 
       first, second and third current sources that respectively provide first, second and third currents;  
       a reference differential pair of first and second reference transistors that is arranged to steer a portion of said third current source to said first and second current sources in response to said differential input signal wherein said first and second reference transistors have first and second reference device sizes; and  
       at least one subtraction differential pair of first and second subtraction transistors that is arranged to steer, in response to said digital command signal, another portion of said third current to said first and second current sources in response to said differential input signal wherein said subtraction differential pair is cross coupled relative to said reference differential pair and wherein said first and second subtraction transistors have first and second subtraction device sizes that are less than said first and second reference device sizes;  
       wherein said differential output current is generated by differences between said first and second currents and those portions of said third current that are coupled to said first and second current sources.  
     
     
       13. The vernier of  claim 12 , wherein said third current substantially equals the sum of said first and second currents. 
     
     
       14. The vernier of  claim 13 , wherein said first and second currents are substantially equal. 
     
     
       15. The vernier of  claim 12 , wherein said first and second reference device sizes are substantially equal and said first and second subtraction device sizes are substantially equal. 
     
     
       16. The vernier of  claim 12 , wherein the first and second subtraction transistors of all of said subtraction differential pairs have substantially equal subtraction device sizes. 
     
     
       17. The vernier of  claim 12 , wherein the first and second subtraction transistors of one of said subtraction differential pairs have subtraction device sizes that that differ from the subtraction device sizes of another of said subtraction differential pairs. 
     
     
       18. The vernier of  claim 12 , further including, for each subtraction differential pair, first and second switches that respond to said digital command signal and are respectively inserted in series with a terminal of that pair's first and second subtraction transistors. 
     
     
       19. The vernier of  claim 12 , wherein said first and second input transistors, said first and second reference transistors and said first and second subtraction transistors are metal-oxide-semiconductor transistors. 
     
     
       20. The vernier of  claim 12 , wherein said first and second input transistors, said first and second reference transistors and said first and second subtraction transistors are bipolar junction transistors. 
     
     
       21. A line driver that responds to a driver input signal and drives a load impedance with a gain that corresponds to a digital command signal, comprising: 
       a vernier that generates a differential current signal in response to said driver input signal;  
       a transformer that has an input winding and also has an output winding for coupling across said load impedance; and  
       first and second multiplying digital-to-analog converters (MDACs) that are each coupled to receive a respective side of said differential current signal and drive a respective side of said input winding;  
       wherein said vernier includes:  
       a) first, second and third current sources that respectively provide first, second and third currents.  
       b) an input differential pair of first and second input transistors arranged to steer said third current along first and second current paths in response to said differential input signal;  
       c) first and second reference transistors that have first and second reference device sizes and that respectively couple said first current path to said first current source and couple said second current path to said second current source; and  
       d) at least one pair of first and second subtraction transistors that have first and second subtraction device sizes that are less than said first and second reference device sizes and that, in response to said digital command signal, respectively couple said first current path to said second current source and couple said second current path to said first current source;  
       wherein said differential output current is generated by differences between said first and second currents and those portions of said third current that are directed towards or away from said first and second current sources.  
     
     
       22. The line driver of  claim 21 , further including a preamplifier inserted between said driver input signal and said vernier. 
     
     
       23. A line driver that responds to a driver input signal and drives a load impedance with a gain that corresponds to a digital command signal, comprising: 
       a vernier that generates a differential current signal in response to said driver input signal;  
       a transformer that has an input winding and also has an output winding for coupling across said load impedance; and  
       first and second multiplying digital-to-analog converters (MDACs) that are each coupled to receive a respective side of said differential current signal and drive a respective side of said input winding;  
       wherein said vernier includes:  
       a) first, second and third current sources that respectively provide first, second and third currents.  
       b) a reference differential pair of first and second reference transistors that is arranged to steer a portion of said third current source to said first and second current sources in response to said differential input signal wherein said first and second reference transistors have first and second reference device sizes; and  
       c) at least one subtraction differential pair of first and second subtraction transistors that is arranged to steer, in response to said digital command signal, another portion of said third current to said first and second current sources in response to said differential input signal wherein said subtraction differential pair is cross coupled relative to said reference differential pair and wherein said first and second subtraction transistors have first and second subtraction device sizes that are less than said first and second reference device sizes;  
       wherein said differential output current is generated by differences between said first and second currents and those portions of said third current that are coupled to said first and second current sources.  
     
     
       24. The line driver of  claim 23 , further including a preamplifier inserted between said driver input signal and said vernier.