US6633468B1ExpiredUtility

High voltage protection circuit for improved oxide reliability

57
Assignee: TEXAS INSTRUMENTS INCPriority: Aug 20, 1999Filed: Jul 5, 2000Granted: Oct 14, 2003
Est. expiryAug 20, 2019(expired)· nominal 20-yr term from priority
H10D 89/811
57
PatentIndex Score
7
Cited by
12
References
13
Claims

Abstract

A structure is designed with an external terminal ( 100 ) and a reference terminal ( 130 ). A first transistor ( 106 ) has a current path coupled to the external terminal and has a first control terminal ( 114 ). A second transistor ( 110 ) has a current path coupled between the current path of the first transistor and the reference terminal and has a second control terminal ( 126 ). A bias circuit comprises a third transistor ( 116 ) having a first conductivity type and a fourth transistor ( 124 ) having a second conductivity type. The third and fourth transistors have respective current paths coupled in series to the reference terminal. The bias circuit is arranged to produce a first voltage at the first control terminal and a second voltage different from the first voltage at the second control terminal.

Claims

exact text as granted — not AI-modified
What is claimed:  
     
       1. A structure, comprising: 
       an external terminal;  
       a supply voltage terminal;  
       a reference terminal;  
       a first transistor having a current path coupled to the external terminal and having a first control terminal;  
       a capacitor coupled between the external terminal and the first control terminal;  
       a second transistor having a current path coupled between the current path of the first transistor and the reference terminal and having a second control terminal; and  
       a bias circuit coupled between the supply voltage terminal and the reference terminal, the bias circuit arranged to produce a first voltage at the first control terminal and a second voltage different from the first voltage at the second control terminal, wherein the bias circuit comprises a third transistor having a first conductivity type and a fourth transistor having a second conductivity type, the fourth transistor having a current path coupled between the first control terminal and the second control terminal.  
     
     
       2. A structure as in  claim 1 , wherein the third transistor has a control terminal coupled to the supply voltage terminal. 
     
     
       3. A structure as in  claim 1 , further comprising a resistor connected between the supply voltage terminal and a control terminal of the fourth transistor. 
     
     
       4. A structure, comprising: 
       an external terminal;  
       a reference terminal;  
       a first transistor having a current path coupled to the external terminal and having a first control terminal;  
       a second transistor having a current path coupled between the current path of the first transistor and the reference terminal and having a second control terminal; and  
       a bias circuit comprising a third transistor having a first conductivity type and a fourth transistor having a second conductivity type, the third and fourth transistors having respective current paths coupled in series to the reference terminal, the bias circuit arranged to produce a first voltage at the first control terminal and a second voltage different from the first voltage at the second control terminal, wherein the current path of the fourth transistor is coupled between the first control terminal and the second control terminal.  
     
     
       5. A structure as in  claim 4 , further comprising a supply voltage terminal, wherein the third transistor has a control terminal coupled to the supply voltage terminal. 
     
     
       6. A structure as in  claim 4 , further comprising a supply voltage terminal and a resistor, wherein the resistor is connected between the supply voltage terminal and a control terminal of the fourth transistor. 
     
     
       7. A structure as in  claim 6 , further comprising a fifth transistor having the second conductivity type and having a current path connected in series with the third and fourth transistors. 
     
     
       8. A structure as in  claim 4 , wherein the first and second transistors have the first conductivity type. 
     
     
       9. A structure as in  claim 4 , further comprising a resistor connected between the second control terminal and the reference terminal. 
     
     
       10. A structure as in  claim 4 , wherein the external terminal is a bond pad. 
     
     
       11. A structure as in  claim 10 , further comprising a protected circuit coupled to the bond pad. 
     
     
       12. A structure as in  claim 11 , wherein the protected circuit comprises a digital signal processing integrated circuit. 
     
     
       13. A structure as in  claim 11 , wherein the protected circuit comprises a dynamic random access memory circuit.

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