Interrupt controller, asic, and electronic equipment

Abstract

An interrupt controller, ASIC, and electronic equipment are provided that make it possible to branch directly to interrupt processing routines at a plurality of locations. When an interrupt controller receives one of IR0 to IR31, it generates an IRQ for a CPU; traps an address AD from the CPU; and after determining that a read instruction for an interrupt vector has been executed, it generates a vector table address VTA corresponding to the interrupt factor with respect to a memory in which the interrupt vector table is stored. The CPU and the memory are connected to a higher-performance ASB, the interrupt controller is connected to a lower-performance APB. A selector selects one of the AD and the VTA, based on a signal from the interrupt controller. A first mode in which the VTA is generated and a second mode in which the interrupt vector is read are switchable.

What is claimed is:  
     
       1. An interrupt controller for controlling interrupt, comprising: 
       means for generating an interrupt request to a processor when an external interrupt request is received;  
       means for trapping an address from the processor, and for determining whether or not the processor which receives the interrupt request has executed a read instruction for an interrupt vector, based on the trapped address; and  
       means for generating a vector table address corresponding to a factor of the external interrupt request, with respect to a memory storing an interrupt vector table, when it is determined that the read instruction for the interrupt vector has been executed.  
     
     
       2. The interrupt controller defined in  claim 1 , wherein the processor and the memory are connected to a higher-performance first bus and the interrupt controller is connected to a lower-performance second bus. 
     
     
       3. An ASIC comprising: 
       the interrupt controller as defined in  claim 2 ;  
       the processor which executes instructions; and  
       the memory which stores at least the interrupt vector table.  
     
     
       4. Electronic equipment comprising: 
       the ASIC as defined in  claim 3 ;  
       input means for inputting data; and  
       output means which outputs at least one of an image and a sound under a control of the ASIC.  
     
     
       5. The interrupt controller defined in  claim 1 , wherein the interrupt controller generates an address switching signal that is output to a selector, which selector selects and outputs one of the address from the processor and the vector table address from the interrupt controller. 
     
     
       6. An ASIC comprising: 
       the interrupt controller as defined in  claim 5 ;  
       the processor which executes instructions; and  
       the memory which stores at least the interrupt vector table.  
     
     
       7. Electronic equipment comprising: 
       the ASIC as defined in  claim 6 ;  
       input means for inputting data; and  
       output means which outputs at least one of an image and a sound under a control of the ASIC.  
     
     
       8. The interrupt controller defined in  claim 1 , further comprising a base register which stores a base address of the vector table address, 
       wherein the interrupt controller generates the vector table address based on the factor of the external interrupt request and the base address from the base register.  
     
     
       9. An ASIC comprising: 
       the interrupt controller as defined in  claim 8 ;  
       the processor which executes instructions; and  
       the memory which stores at least the interrupt vector table.  
     
     
       10. Electronic equipment comprising: 
       the ASIC as defined in  claim 9 ;  
       input means for inputting data; and  
       output means which outputs at least one of an image and a sound under a control of the ASIC.  
     
     
       11. The interrupt controller defined in  claim 1 , comprising a first mode and a second mode which are switchable therebetween, processing that traps the address from the processor and generates the vector table address being enabled in the first mode and being disabled in the second mode. 
     
     
       12. An ASIC comprising: 
       the interrupt controller as defined in  claim 11 ;  
       the processor which executes instructions; and  
       the memory which stores at least the interrupt vector table.  
     
     
       13. Electronic equipment comprising: 
       the ASIC as defined in  claim 12 ;  
       input means for inputting data; and  
       output means which outputs at least one of an image and a sound under a control of the ASIC.  
     
     
       14. An ASIC comprising: 
       the interrupt controller as defined in  claim 1 ;  
       the processor which executes instructions; and  
       the memory which stores at least the interrupt vector table.  
     
     
       15. Electronic equipment comprising: 
       the ASIC as defined in  claim 14 ;  
       input means for inputting data; and  
       output means which outputs at least one of an image and a sound under a control of the ASIC.