Method and apparatus for enabling extests to be performed in AC-coupled systems

Abstract

A method and apparatus are provided for enabling a Joint Test Access Group (JTAG)-type EXTEST to be performed in an alternating current (AC)-coupled system in order to test one or more AC-coupled connections on a printed circuit board (PCB). Direct current (DC)-restore logic receives an AC-coupled signal that corresponds to an EXTEST test pattern output from a transmitting JTAG-compliant integrated circuit (IC), and converts the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC.

What is claimed is:  
     
       1. An apparatus for enabling a Joint Test Access Group (JTAG)-type EXTEST to be performed in an alternating current (AC)-coupled system in order to test one or more connections on a printed circuit board (PCB), the apparatus comprising: 
       a direct current (DC)-restore logic, the DC-restore logic receiving an AC-coupled signal, the AC-coupled signal corresponding to an EXTEST test pattern output from a transmitting JTAG-compliant integrated circuit (IC), the DC-restore logic converting the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC.  
     
     
       2. The apparatus of  claim 1 , wherein the the JTAG logic of the JTAG-compliant receiving IC comprises the DC-restore logic. 
     
     
       3. The apparatus of  claim 1 , wherein the DC-restore logic is located on the PCB external to the JTAG-compliant receiving IC. 
     
     
       4. The apparatus of  claim 1 , wherein the EXTEST test pattern is being transmitted over a connection from the transmitting JTAG-compliant IC to the receiving JTAG-compliant IC, the AC-coupled signal being produced when a DC EXTEST test pattern output from the transmitting JTAG-compliant integrated circuit IC encounters an AC-coupling element in the connection. 
     
     
       5. The apparatus of  claim 4 , wherein the DC-restore logic is coupled to the connection between the AC-coupling element and the JTAG logic of the receiving JTAG-compliant IC. 
     
     
       6. The apparatus of  claim 1 , wherein the DC signal output from the JTAG-compliant transmitting IC corresponds to a series of digital 1s and 0s, the digital 1s and 0s corresponding to the EXTEST test pattern output from the transmitting JTAG-compliant IC, and wherein the DC signal resulting from the conversion of the AC-coupled signal by the DC-restore logic corresponds to the series of digital 1s and 0s output from the transmitting JTAG-compliant IC. 
     
     
       7. The apparatus of  claim 1 , wherein the DC-restore logic comprises at least a first inverter and a second inverter, the first inverter receiving the AC-coupled signal and inverting the AC-coupled signal when the AC-coupled signal passes a first threshold value of the first inverter to produce a first inverted signal, the first inverter outputting the said first inverted signal, the second inverter receiving said first inverted signal and inverting the first inverted signal to produce an input signal to the first inverter that maintains the first inverter at a first state until the AC-coupled signal changes polarity and passes a second threshold value of the first inverter, wherein when the AC-coupled signal changes polarity and passes the second threshold value of the first inverter, the first inverter outputs a second inverted output signal, the second inverter receiving the second inverted output signal and inverting the received second inverted output signal that is input to the first inverter and that maintains a second state of the first inverter until the AC-coupled signal changes polarity and passes the first threshold value of the first inverter. 
     
     
       8. The apparatus of  claim 7 , wherein the JTAG logic of the receiving JTAG-compliant IC comprises the DC-restore logic. 
     
     
       9. The apparatus of  claim 1 , wherein the DC-restore logic comprises a Schmidt trigger, the Schmidt trigger receiving the AC-coupled signal and converting the AC-coupled signal into a DC signal having a first state when the AC-coupled signal exceeds a first hysteresis level of the Schmidt trigger and converting the AC-coupled signal into a DC signal having a second state when the AC-coupled signal exceeds a second hysteresis level of the Schmidt trigger, and wherein the first state is maintained even after the AC-coupled signal has dropped below the first hysteresis level and changes to the second state only when the AC-coupled signal has dropped below the second hysteresis level, and wherein the second state is maintained even after the AC-coupled signal has exceeded above the second hysteresis level and changes to the first state only when the AC-coupled signal has exceeded above the first hysteresis level. 
     
     
       10. The apparatus of  claim 9 , wherein the JTAG logic of the receiving JTAG-compliant IC comprises the DC-restore logic. 
     
     
       11. A method for enabling a Joint Test Access Group (JTAG)-type EXTEST to be performed in an alternating current (AC)-system in order to test one or more AC-coupled connections on a printed circuit board (PCB), the method comprising the steps of: 
       providing direct current (DC)-restore logic, the DC-restore logic receiving an AC-coupled signal, the AC-coupled signal corresponding to an EXTEST test pattern output from a transmitting JTAG-compliant integrated circuit (IC); and  
       converting the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC, the AC-coupled signal being converted by the DC-restore logic.  
     
     
       12. The method of  claim 11 , wherein the JTAG logic of the JTAG-compliant receiving IC comprises the DC-restore logic. 
     
     
       13. The method of  claim 11 , wherein DC-restore logic is located on the PCB external to the JTAG-compliant receiving IC. 
     
     
       14. The method of  claim 11 , wherein the EXTEST test pattern is being transmitted over a connection from the transmitting JTAG-compliant IC to the receiving JTAG-compliant IC, the AC-coupled signal being produced when a DC EXTEST test pattern output from the transmitting JTAG-compliant integrated circuit IC encounters an AC-coupling element in the connection. 
     
     
       15. The method of  claim 14 , wherein the DC-restore logic is coupled to the connection between the AC-coupling element and the JTAG logic of the receiving JTAG-compliant IC. 
     
     
       16. The method of  claim 11 , wherein the DC signal output from the JTAG-compliant transmitting IC corresponds to a series of digital 1s and 0s, the digital 1s and 0s corresponding to the EXTEST test pattern output from the transmitting JTAG-compliant IC, and wherein the DC signal resulting from the conversion of the AC-coupled signal by the DC-restore logic corresponds to the series of digital 1s and 0s output from the transmitting JTAG-compliant IC. 
     
     
       17. The method of  claim 11 , wherein the DC-restore logic comprises at least a first inverter and a second inverter, the first inverter receiving the AC-coupled signal and inverting the AC-coupled signal when the AC-coupled signal passes a first threshold value of the first inverter to produce a first inverted signal, the first inverter outputting the said first inverted signal, the second inverter receiving said first inverted signal and inverting the first inverted signal to produce an input signal to the first inverter that maintains the first inverter at a first state until the AC-coupled signal changes polarity and passes a second threshold value of the first inverter, wherein when the AC-coupled signal changes polarity and passes the second threshold value of the first inverter, the first inverter outputs a second inverted output signal, the second inverter receiving the second inverted output signal and inverting the received second inverted output signal that is input to the first inverter and that maintains a second state of the first inverter until the AC-coupled signal changes polarity and passes the first threshold value of the first inverter. 
     
     
       18. The method of  claim 17 , wherein the JTAG logic of the receiving JTAG-compliant IC comprises the DC-restore logic. 
     
     
       19. The method of  claim 11 , wherein the DC-restore logic comprises a Schmidt trigger, the Schmidt trigger receiving the AC-coupled signal and converting the AC-coupled signal into a DC signal having a first state when the AC-coupled signal exceeds a first hysteresis level of the Schmidt trigger and converting the AC-coupled signal into a DC signal having a second state when the AC-coupled signal exceeds a second hysteresis level of the Schmidt trigger, and wherein the first state is maintained even after the AC-coupled signal has dropped below the first hysteresis level and changes to the second state only when the AC-coupled signal has dropped below the second hysteresis level, and wherein the second state is maintained even after the AC-coupled signal has exceeded above the second hysteresis level and changes to the first state only when the AC-coupled signal has exceeded above the first hysteresis level. 
     
     
       20. The method of  claim 19 , wherein the JTAG logic of the receiving JTAG-compliant IC comprises the DC-restore logic.