MRAM memory array having merged word lines

Abstract

A method and system for providing and using a magnetic memory including magnetic memory cells is disclosed. The method and system include providing a magnetic tunneling junction including a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The magnetic memory cell is coupled to a merged word line and a bit line. The merged word line selects the magnetic memory cell during a reading and carries a write current for the magnetic memory cell during writing. The bit line provides current to the magnetic memory cell during the reading and the writing. The currents provided by the bit line and the merged word line during writing allow data to be written to the magnetic memory cell.

What is claimed is:  
     
       1. A magnetic memory cell comprising: 
       a magnetic tunneling junction including a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer;  
       wherein the magnetic memory cell is coupled to a merged word line, the merged word line being configured for selecting the magnetic memory cell during a reading and for carrying a write current for the magnetic memory cell during a writing; and  
       wherein the magnetic memory cell is coupled to a bit line for providing current to the magnetic memory cell during the reading and the writing.  
     
     
       2. The magnetic memory cell of  claim 1  further comprising: 
       a transistor coupled to the magnetic tunneling junction, the transistor including a source, a drain and a gate.  
     
     
       3. The magnetic memory cell of  claim 2  wherein the merged word line is coupled to the gate of the transistor. 
     
     
       4. The magnetic memory cell of  claim 1  wherein the bit line is coupled to the magnetic tunneling junction. 
     
     
       5. A magnetic memory comprising: 
       a plurality of memory cells arranged in an array including a plurality of rows and a plurality of columns, each of the plurality of memory cells including at least a magnetic tunneling junction;  
       a plurality of merged word lines coupled to the plurality of rows, the plurality of merged word lines for selecting between the plurality of rows during a reading and for carrying a write current to a selected row of the plurality of rows during writing;  
       a plurality of bit lines coupled to the plurality of columns, the plurality of bit lines for selecting between the plurality of columns during the reading and the writing.  
     
     
       6. The magnetic memory of  claim 5  wherein each of the plurality of memory cells includes a transistor coupled to the magnetic tunneling junction, the transistor including a source, a drain and a gate. 
     
     
       7. The magnetic memory of  claim 6  wherein the merged word line is coupled to the gate of the transistor. 
     
     
       8. The magnetic memory of  claim 5  wherein the bit line is coupled to the magnetic tunneling junction. 
     
     
       9. A method for utilizing a magnetic memory comprising the steps of: 
       (a) in a write mode, writing to a first portion of a plurality of memory cells by providing a first current in a merged word line of a plurality of merged word lines and a second current in a bit line of a plurality of bit lines, the plurality of memory cells arranged in an array including a plurality of rows and a plurality of columns, each of the plurality of memory cells including a magnetic tunneling junction;  
       (b) in a read mode, reading from a second portion of the plurality of memory cells by providing a read current in the bit line of the plurality of bit lines and by selecting a row using the merged word line of the plurality of merged word lines.  
     
     
       10. The method of  claim 9  wherein each of the plurality of memory cells includes a transistor coupled to the magnetic tunneling junction, the transistor including a source, a drain and a gate. 
     
     
       11. The method of  claim 10  wherein the merged word line is coupled to the gate of the transistor. 
     
     
       12. The method of  claim 9  wherein the bit line is coupled to the magnetic tunneling junction.