Process compensated phase locked loop

Abstract

A phase locked loop having a voltage-controlled oscillator is adjusted to compensate for process variations in the formation of the phase locked loop. In each instance of the phase locked loop, the center frequency of the voltage-controlled oscillator is adjusted using a bias signal while holding the control voltage of the voltage-controlled oscillator at zero. Then, the control voltage of the voltage-controlled oscillator is set to a different value and the gain of the voltage-controlled oscillator is adjusted.

What is claimed is:  
     
       1. A phase locked loop configured to receive a reference signal and to generate a PLL output clock signal, the phase locked loop comprising: 
       a phase and frequency comparator coupled to receive the reference clock signal and a feedback clock signal;  
       a charge pump coupled to the phase and frequency comparator;  
       a voltage controlled oscillator coupled to the charge pump and coupled to generate the PLL output clock signal;  
       a clock divider coupled to the voltage controlled oscillator and the phase and frequency comparator; and  
       a PLL process variation compensation unit coupled to control a center frequency and a gain of the voltage controlled oscillator, wherein the PLL process variation compensation unit is operably configured to control the center frequency by:  
       setting a divisor of the clock divider to a first value; and  
       adjusting a bias signal of a voltage to current converter until frequency of the feedback clock signal is approximately equal to frequency of the reference clock signal.  
     
     
       2. The phase locked loop of  claim 1 , further comprising a loop filter coupled between the voltage controlled oscillator and the charge pump. 
     
     
       3. The phase locked loop of  claim 2 , further comprising a loop filter bypass coupled between the voltage controlled oscillator and the loop filter. 
     
     
       4. The phase locked loop of  claim 1 , wherein the PLL process variations compensation unit further comprises: 
       a center frequency control circuit coupled to control the center frequency of the voltage controlled oscillator; and  
       a gain control circuit coupled to control the gain of the voltage controlled oscillator.  
     
     
       5. The phase locked loop of  claim 4 , wherein the PLL process variations compensation unit further comprises a compensation control unit coupled to the center frequency control circuit, the gain control circuit and the phase and frequency comparator. 
     
     
       6. The phase locked loop of  claim 4 , wherein the gain control circuit controls a transconductance value in the voltage controlled oscillator. 
     
     
       7. A method for compensating for process variations in a phase locked loop having a phase and frequency comparator, a charge pump, a voltage controlled oscillator and a clock divider, the method comprising: 
       adjusting a center frequency of the voltage controlled oscillator by:  
       setting a divisor of the clock divider to a first value; and  
       adjusting a bias signal of a voltage to current converter of the voltage controlled oscillator until frequency of a feedback clock signal is approximately equal to frequency of a reference clock signal; and  
       adjusting a gain of the voltage controlled oscillator.  
     
     
       8. The method of  claim 7 , wherein the adjusting a center frequency of the voltage controlled oscillator comprises: 
       setting a control voltage of the voltage controlled oscillator to zero prior to adjusting the bias signal.  
     
     
       9. The method of  claim 8 , wherein the adjusting the bias signal of the voltage controlled oscillator until the frequency of the feedback clock signal is approximately equal to the frequency of the reference clock signal comprises: 
       setting the bias signal to an initial value;  
       comparing the frequency of the reference clock signal with the frequency of the feedback clock signal; and  
       incrementing the bias signal when the frequency of the feedback clock signal is less than the frequency of the reference clock signal.  
     
     
       10. The method of  claim 7 , wherein the adjusting a gain of the voltage controlled oscillator comprises: 
       setting the gain of the voltage controlled oscillator to an initial value;  
       comparing the frequency of the reference clock signal with the frequency of the feedback clock signal; and  
       incrementing the gain of the voltage controlled oscillator when the frequency of the feedback clock signal is less than the frequency of the reference clock signal.  
     
     
       11. The method of  claim 10 , wherein the adjusting a gain of the voltage controlled oscillator further comprises setting a divisor of the clock divider to a second value. 
     
     
       12. The method of  claim 10 , wherein the incrementing the gain of the voltage controlled oscillator when the frequency of the feedback clock signal is less than the frequency of the reference clock signal comprises increasing a transconductance of a voltage to current converter in the voltage controlled oscillator. 
     
     
       13. A system for compensating for process variations in a phase locked loop having a phase and frequency comparator, a charge pump, a voltage controlled oscillator and a clock divider, the method comprising: 
       means for adjusting a center frequency of the voltage controlled oscillator by:  
       setting a divisor of the clock divider to a first value; and  
       adjusting a bias signal of a voltage to current converter of the voltage controlled oscillator until frequency of a feedback clock signal is approximately equal to frequency of a reference clock signal; and  
       means for adjusting a gain of the voltage controlled oscillator.  
     
     
       14. The system of  claim 13 , wherein the means for adjusting a center frequency of the voltage controlled oscillator comprises: 
       means for setting a control voltage of the voltage controlled oscillator to zero prior to the adjusting of the bias signal.  
     
     
       15. The system of  claim 14 , wherein the means for adjusting the bias signal of the voltage controlled oscillator until the frequency of the feedback clock signal is approximately equal to the frequency of the reference clock signal comprises: 
       means for setting the bias signal to an initial value;  
       means for comparing the frequency of the reference clock signal with the frequency of the feedback clock signal; and  
       means for incrementing the bias signal when the frequency of the feedback clock signal is less than the frequency of the reference clock signal.  
     
     
       16. The system of  claim 13 , wherein the means for adjusting a gain of the voltage controlled oscillator comprises: 
       means for setting the gain of the voltage controlled oscillator to an initial value;  
       means for comparing the frequency of the reference clock signal with the frequency of the feedback clock signal; and  
       means for incrementing the gain of the voltage controlled oscillator when the frequency of the feedback clock signal is less than the frequency of the reference clock signal.  
     
     
       17. The system of  claim 16 , wherein the means for adjusting a gain of the voltage controlled oscillator further comprises means for setting a divisor of the clock divider to a second value. 
     
     
       18. The system of  claim 16 , wherein the means for incrementing the gain of the voltage controlled oscillator when the frequency of the feedback clock signal is less than the frequency of the reference clock signal comprises means for increasing a transconductance of a voltage to current converter in the voltage controlled oscillator.