Optimize global net timing with repeater buffers

Abstract

A method, system, and program product for designing an electronic circuit. The electronic circuit has a source component, a sink component and a wire connecting the source and sink components. In one aspect, the wire is divided into wire segments and repeater buffers are added to connect the wire segments. The number of repeater buffers is based on the calculated delay of the global net. In another aspect, the metal routes of the wire are widened to reduce delays on a global net. In these ways, the timing goal of the electronic circuit is met, such that an operation in the electronic circuit will complete within one clock cycle.

What is claimed is:  
     
       1. A computer-executed method for designing an electronic circuit comprising a source component, a sink component and a plurality of wire segments connecting the source and sink components, wherein the method comprises: 
       calculating a number of repeater buffers to connect the wire segments, wherein the number is optimized to meet a timing goal of the electronic circuit, and wherein the calculating is based on a capacitance rise wherein the capacitance rise is determined based on a capacitance, a resistance, and a length of at least one of the wire segments; and  
       adding the buffers to a netlist.  
     
     
       2. The method of  claim 1 , further comprising: 
       widening a width of the wire segments, wherein the width is optimized to meet the timing goal of the electronic circuit.  
     
     
       3. The method of  claim 1 , wherein the repeater buffer comprises: 
       two inverters connected in series.  
     
     
       4. The method of  claim 1 , wherein the timing goal is met when an operation will complete in less than one clock cycle. 
     
     
       5. The method of  claim 1 , further comprising: 
       when the source component is a random logic module, determining whether to add a source buffer based on the length and width of the source component.  
     
     
       6. The method of  claim 1 , further comprising: 
       when the sink component is a random logic module, determining whether to add a sink buffer based on the length and width of the source component.  
     
     
       7. The method of  claim 1 , wherein the calculating step optimizes the number of repeater buffers based on the resistance, length, and capacitance of the wire. 
     
     
       8. A program product for designing an electronic circuit comprising a source component, a sink component and a plurality of wire segments connecting the source and sink components, wherein the program product comprises a signal-bearing media bearing instructions, wherein the instructions, when executed by a computer, comprise: 
       calculating a number of repeater buffers to connect the wire segments, wherein the number is optimized to meet a timing goal of the electronic circuit, and wherein the calculating is based on a capacitance rise wherein the capacitance rise is determined based on a capacitance, a resistance, and a length of at least one of the wire segments; and  
       adding the buffers to a netlist.  
     
     
       9. The program product of  claim 8 , further comprising: 
       widening a width of the wire segments, wherein the width is optimized to meet the timing goal of the electronic circuit.  
     
     
       10. The program product of  claim 8  wherein the repeater buffer comprises: 
       two inverters connected in series.  
     
     
       11. The program product of  claim 8  wherein the timing goal is met when an operation will complete in less than one clock cycle. 
     
     
       12. The program product of  claim 8  further comprising: 
       when the source component is a random logic module, determining whether to add a source buffer based on the length and width of the source component.  
     
     
       13. The program product of  claim 8  further comprising: 
       when the sink component is a random logic module, determining whether to add a sink buffer based on the length and width of the source component.  
     
     
       14. The program product of  claim 8  wherein the calculating element optimizes the number of repeater buffers based on the resistance, length, and capacitance of the wire. 
     
     
       15. A computer system for designing an electronic circuit comprising a source component, a sink component and a plurality of wire segments connecting the source and sink components, wherein the computer system comprises: 
       a processor; and  
       memory coupled to the processor, wherein the memory contains instructions, which when executed on the processor comprise:  
       calculating a number of repeater buffers to connect the wire segments, wherein the number is optimized to meet a timing goal of the electronic circuit, and wherein the calculating is based on a capacitance rise wherein the capacitance rise is determined based on a capacitance, a resistance, and a length of at least one of the wire segments, and  
       adding the buffers to a netlist.  
     
     
       16. The computer system of  claim 15 , further comprising: 
       widening a width of the wire segments, wherein the width is optimized to meet the timing goal of the electronic circuit.  
     
     
       17. The computer system of  claim 15  wherein the repeater buffer comprises: 
       two inverters connected in series.  
     
     
       18. The computer system of  claim 15  wherein the timing goal is met when an operation will complete in less than one clock cycle. 
     
     
       19. The computer system of  claim 15  further comprising: 
       when the source component is a random logic module, determining whether to add a source buffer based on the length and width of the source component.  
     
     
       20. The computer system of  claim 15  further comprising: 
       when the sink component is a random logic module, determining whether to add a sink buffer based on the length and width of the source component.  
     
     
       21. The computer system of  claim 15  wherein the calculating element optimizes the number of repeater buffers based on the resistance, length, and capacitance of the wire.