Method and system for low power, low jitter, wide range, self-adaptive multi-frequency phase locked loop

Abstract

A self-adaptive method for controlling a self-biased PLL system is disclosed. The method comprises providing an application-dependent input frequency; and providing an application-dependent number N representing the ratio between the output frequency and the application-dependent input frequency to the PLL system. In a system and method in accordance with the present invention, the bandwidth and damping factor are tracked, not only with the input frequency but with the divider ratio as well. Therefore, jitter is minimized for any operating condition (i.e., input frequency variations [N]). The charge-pump current is made to be proportional to the VCO current ID and inversely proportional to the frequency range N; and the loop filter resistor is made to be inversely proportional to the square root of the VCO current ID and proportional to N. In so doing, the bandwidth and damping factors can be tracked more comprehensively.

What is claimed is:  
     
       1. A self-adaptive method for controlling a self-biased PLL system, the method comprising the steps of: 
       (a) providing an application-dependent input reference frequency;  
       (b) providing a variable application-dependent number N where N is a decimal number representing the ratio between an output frequency and the application-dependent input frequency to the PLL systems;  
       (c) synthesizing an output signal whose frequency is N times that of the application-dependent input reference frequency by a phase locked loop (PLL);  
       (d) generating a first charge pump output signal in response to a phase-frequency detector output signal by a first charge pump coupled to a phase-frequency detector; and  
       (e) generating a second charge pump output signal in response to the phase-frequency detector output signal by a second charge pump coupled to said phase-frequency detector, wherein the second charge pump has an effective resistance suitable for adjusting a bandwidth and a damping factor that are each tracked with respect to any of a number of process or voltage or temperature variations.  
     
     
       2. The method of  claim 1 , further comprising: 
       (f) aligning the application-dependent frequency input reference signal having a reference phase with a feedback signal having a feedback phase.  
     
     
       3. The method  claim 1 , further comprising: 
       (g) generating a decoded output representing the application-dependent number N between the said output frequency and the said input frequency.  
     
     
       4. The method of  claim 1 , further comprising: 
       (h) comparing the reference phase and the feedback phase; and  
       (i) generating a phase-frequency detector output signal that is proportional to a difference between the reference phase and the feedback phase based upon the comparing (h).  
     
     
       5. The method of  claim 1 , further comprising: 
       (k) filtering the first charge pump output signal by a loop filter coupled to said first charge pump, thereby producing an integral control voltage.  
     
     
       6. A self-biased PLL system comprising: 
       a detector for comparing a reference frequency to a feedback frequency,  
       at least one charge pump coupled to a phase detector;  
       a filter coupled to the at least one charge pump;  
       a bias generator coupled to the filter and to the at least one charge pump;  
       a voltage controlled oscillator (VCO) coupled to the bias generator;  
       a counter coupled to the VCO and the phase detector, for providing the feedback frequency; and  
       a decoder for controlling the counter and the at least one charge pump, wherein the self-biased PLL is suitably disposed to be utilized at a plurality of frequencies.  
     
     
       7. The system of  claim 6  wherein a bandwidth and a damping factor is each tracked with respect to process, voltage and temperature variations. 
     
     
       8. The system of  claim 6  wherein the decoder allows a ratio (N) between an output frequency and an input frequency to be variable and application dependent. 
     
     
       9. The system of  claim 7  wherein an application dependent frequency phase is aligned with a feedback frequency phase. 
     
     
       10. The system of  claim 9  wherein a phase frequency detector provides a phase frequency detector output signal that is proportional to a difference between the reference phase and the feedback phase. 
     
     
       11. The system of  claim 9 , further comprising a first charge pump of the at least one charge pump arranged to provide a first charge pump output signal in response to the phase-frequency detector output signal. 
     
     
       12. The system of  claim 9 , wherein the filter produces an integral control voltage. 
     
     
       13. The system of  claim 9 , further comprises a second charge pump of the at least one charge pump coupled to said phase-frequency detector for generating a second charge pump output signal in response to the phase-frequency detector output signal, said second charge pump having an effective resistance for adjusting a bandwidth and a damping factor.