Semiconductor memory device and method for producing the same

Abstract

A semiconductor memory device able to increase the effective area of a capacitor in a memory cell and ensure a sufficient amount of charge contained in a read signal while maintaining the smallest cell area and a method for producing the same, wherein a first node electrode, a first ferroelectric film, and plate electrodes form four ferroelectric capacitors, plate electrodes, a second ferroelectric film, and a second node electrode form other four ferroelectric capacitors, the first node electrode is electrically connected to the second node electrode, a capacitor below a plate electrode is connected in parallel with the capacitor above the plate electrode, and these two capacitors connected in parallel form a memory cell storing 1 bit of data.

What is claimed is:  
     
       1. A semiconductor memory device comprising: 
       a MIS transistor for selecting a memory cell;  
       a common node electrode electrically connected with an impurity diffusing region of the MIS transistor;  
       a bit line electrically connected with another impurity diffusing region of the MIS transistor; and  
       a plurality of storage means connected to the common node electrode, wherein  
       each said storage means includes a plurality of capacitors electrically connected with each other in parallel.  
     
     
       2. A semiconductor memory device as set forth in  claim 1 , wherein 
       said a plurality of storage means are formed by stacking a plurality of capacitor layers each including said common node electrode, a plate electrode layer having a plurality of plate electrodes each facing the common node electrode, and a dielectric film between the common node electrode and the plate electrode layer, where  
       in two adjacent capacitor layers, the common node electrode, the dielectric film, and the plate electrode layer are arranged in reverse order.  
     
     
       3. A semiconductor memory device as set forth in  claim 2 , wherein 
       said two adjacent capacitor layers share the same common node electrode or the same plate electrode layer.  
     
     
       4. A semiconductor memory device as set forth in  claim 3 , wherein 
       said plate electrodes in different capacitor layers included in each said storage means are connected with each other, and  
       said common node electrodes in different capacitor layers are connected with each other.  
     
     
       5. A semiconductor memory device comprising a plurality of memory cell blocks each including 
       a MIS transistor for selecting a memory cell;  
       a common node electrode electrically connected with an impurity diffusing region of the MIS transistor;  
       a bit line electrically connected with another impurity diffusing region of the MIS transistor; and  
       a plurality of storage means connected to the common node electrode, wherein  
       each said storage means includes a plurality of capacitors electrically connected with each other in parallel, and  
       said common node electrodes of different memory cell blocks are stacked so as to overlap each other.  
     
     
       6. A semiconductor memory device as set forth in  claim 5 , wherein 
       each of said plurality of storage means in each said memory cell block is formed by stacking a plurality of capacitor layers each including said common node electrode, a plate electrode layer having a plurality of plate electrodes each facing the common node electrode, and a dielectric film between the common node electrode and the plate electrode layer, and  
       the common node electrode, the dielectric film, and the plate electrode layer are arranged in reverse order in two adjacent capacitor layers.  
     
     
       7. A semiconductor memory device as set forth in  claim 6 , wherein 
       said two adjacent capacitor layers share the same common node electrode or the same plate electrode layer.  
     
     
       8. A semiconductor memory device as set forth in  claim 7 , wherein 
       said plate electrodes in different capacitor layers included in each said storage means are connected with each other, and  
       said common node electrodes in different said capacitor layers are connected with each other.