Extended voltage range level shifter

Abstract

An extended voltage range level shifter is provided that includes an input inverter and first and second circuit branches. The input inverter includes thin-gate devices, is coupled to an internal power supply, and is operable to receive internal data and to generate inverted internal data. The first circuit branch includes a p-type, thick-gate transistor that has a source coupled to an external power supply; a first n-type, thick-gate transistor that has a drain coupled to a drain of the p-type transistor and a gate operable to receive a reference voltage that is less than the external power supply and greater than the internal power supply; and a second n-type, thin-gate transistor that has a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the internal data. The second circuit branch also includes a p-type, thick-gate transistor that has a source coupled to the external power supply, a drain coupled to a gate of the p-type transistor for the first circuit branch, and a gate coupled to the drain of the p-type transistor for the first circuit branch; a first n-type, thick-gate transistor that has a drain coupled to a drain of the p-type transistor and a gate operable to receive the reference voltage; and a second n-type, thin-gate transistor that has a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the inverted internal data.

What is claimed is:  
     
       1. An extended voltage range level shifter, comprising: 
       an input inverter comprising thin-gate devices, the input inverter coupled to an internal power supply associated with an internal voltage domain and operable to receive internal data in the internal voltage domain and to generate inverted internal data;  
       a first circuit branch comprising A) a p-type, thick-gate transistor having a source coupled to an external power supply associated with an external voltage domain, B) a first n-type, thick-gate transistor having a drain coupled to a drain of the p-type transistor and a gate operable to receive a reference voltage, the reference voltage less than the external power supply and greater than the internal power supply, and C) a second n-type, thin-gate transistor having a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the internal data; and  
       a second circuit branch comprising A) a p-type, thick-gate transistor having a source coupled to the external power supply, a drain coupled to a gate of the p-type transistor for the first circuit branch, and a gate coupled to the drain of the p-type transistor for the first circuit branch, B) a first n-type, thick-gate transistor having a drain coupled to a drain of the p-type transistor and a gate operable to receive the reference voltage, and C) a second n-type, thin-gate transistor having a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the inverted internal data.  
     
     
       2. The level shifter of  claim 1 , further comprising a reference voltage generator coupled to the gates of the first n-type transistors for the first and second circuit branches, the reference voltage generator operable to generate the reference voltage and provide the reference voltage to the gates of the first n-type transistors for the first and second circuit branches. 
     
     
       3. The level shifter of  claim 2 , the reference voltage generator comprising: 
       a first p-type, thick-gate transistor having a source coupled to the external power supply, a gate, and a drain coupled to the gate;  
       a second p-type, thick-gate transistor having a source coupled to the drain of the first p-type transistor, a gate, and a drain coupled to the gate;  
       a third p-type, thick-gate transistor having a source coupled to the drain of the second p-type transistor, a gate operable to receive a mode indicator, and a drain coupled to ground, the third p-type transistor comprising a length x;  
       a fourth p-type, thick-gate transistor having a source coupled to the drain of the second p-type transistor, a gate operable to receive an inverted mode indicator, and a drain coupled to ground, the fourth p-type transistor comprising a specified percentage of the length x; and  
       wherein the reference voltage generator is operable to generate the reference voltage at the drain of the first p-type transistor.  
     
     
       4. The level shifter of  claim 3 , the specified percentage of the length x comprising approximately 75%. 
     
     
       5. The level shifter of  claim 2 , the reference voltage generator comprising: 
       a first p-type, thick-gate transistor having a source coupled to the external power supply, a gate, and a drain coupled to the gate;  
       a second p-type, thick-gate transistor having a source coupled to the drain of the first p-type transistor, a gate, and a drain coupled to the gate;  
       a third p-type, thick-gate transistor having a source coupled to the drain of the second p-type transistor, a gate operable to receive a mode indicator, and a drain coupled to ground;  
       a fourth p-type, thick-gate transistor having a source coupled to the drain of the second p-type transistor and a gate operable to receive an inverted mode indicator;  
       a fifth p-type, thin-gate transistor having a source coupled to a drain for the fourth p-type transistor, a gate coupled to ground, and a drain coupled to ground, the fifth p-type transistor comprising a length x, the third p-type transistor comprising a first specified multiple of the length x, and the fourth p-type transistor comprising a second specified multiple of the length x;  
       a charge assist circuit coupled to the drain of the first p-type transistor;  
       a capacitor coupled to the drain of the first p-type transistor; and  
       wherein the reference voltage generator is operable to generate the reference voltage at the drain of the first p-type transistor.  
     
     
       6. The level shifter of  claim 5 , the first specified multiple of the length x comprising approximately two and the second specified multiple of the length x comprising approximately three. 
     
     
       7. The level shifter of  claim 1 , further comprising an output inverter coupled to the drain of the first n-type transistor for the first circuit branch, the output inverter operable to receive a signal from the drain of the first n-type transistor for the first circuit branch and to invert the signal to generate external data in the external voltage domain. 
     
     
       8. The level shifter of  claim 7 , the output inverter comprising: 
       a p-type, thick-gate transistor having a source coupled to the external power supply and a gate coupled to the drain of the first n-type transistor for the first circuit branch;  
       an n-type, thick-gate transistor having a drain coupled to a drain for the p-type transistor, a source coupled to ground, and a gate coupled to the drain of the first n-type transistor for the first circuit branch; and  
       wherein the output inverter is operable to generate the external data at the drains of the p-type and n-type transistors.  
     
     
       9. The level shifter of  claim 1 , the input inverter comprising: 
       a p-type, thin-gate transistor having a source coupled to the internal power supply and a gate operable to receive the internal data;  
       an n-type, thin-gate transistor having a drain coupled to a drain for the p-type transistor, a source coupled to ground, and a gate operable to receive the internal data; and  
       wherein the input inverter is operable to generate the inverted internal data at the drains of the p-type and n-type transistors.  
     
     
       10. The level shifter of  claim 1 , the internal voltage domain comprising a swing voltage of less than 1.0 volt, the external voltage domain comprising a swing voltage of at least 3.0 volts, and the reference voltage comprising about 1.6 to about 2.2 volts. 
     
     
       11. An integrated circuit comprising: 
       core processing circuitry operable to function in an internal voltage domain;  
       output stage circuitry operable to function in an external voltage domain; and  
       an extended voltage range level shifter comprising:  
       an input inverter comprising thin-gate devices, the input inverter coupled to an internal power supply associated with an internal voltage domain and operable to receive internal data in the internal voltage domain and to generate inverted internal data;  
       a first circuit branch comprising A) a p-type, thick-gate transistor having a source coupled to an external power supply associated with an external voltage domain, B) a first n-type, thick-gate transistor having a drain coupled to a drain of the p-type transistor and a gate operable to receive a reference voltage, the reference voltage less than the external power supply and greater than the internal power supply, and C) a second n-type, thin-gate transistor having a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the internal data; and  
       a second circuit branch comprising A) a p-type, thick-gate transistor having a source coupled to the external power supply, a drain coupled to a gate of the p-type transistor for the first circuit branch, and a gate coupled to the drain of the p-type transistor for the first circuit branch, B) a first n-type, thick-gate transistor having a drain coupled to a drain of the p-type transistor and a gate operable to receive the reference voltage, and C) a second n-type, thin-gate transistor having a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the inverted internal data.  
     
     
       12. The integrated circuit of  claim 11 , the level shifter further comprising a reference voltage generator coupled to the gates of the first n-type transistors for the first and second circuit branches, the reference voltage generator operable to generate the reference voltage and provide the reference voltage to the gates of the first n-type transistors for the first and second circuit branches. 
     
     
       13. The integrated circuit of  claim 12 , the reference voltage generator comprising: 
       a first p-type, thick-gate transistor having a source coupled to the external power supply, a gate, and a drain coupled to the gate;  
       a second p-type, thick-gate transistor having a source coupled to the drain of the first p-type transistor, a gate, and a drain coupled to the gate;  
       a third p-type, thick-gate transistor having a source coupled to the drain of the second p-type transistor, a gate operable to receive a mode indicator, and a drain coupled to ground, the third p-type transistor comprising a length x;  
       a fourth p-type, thick-gate transistor having a source coupled to the drain of the second p-type transistor, a gate operable to receive an inverted mode indicator, and a drain coupled to ground, the fourth p-type transistor comprising a specified percentage of the length x; and  
       wherein the reference voltage generator is operable to generate the reference voltage at the drain of the first p-type transistor.  
     
     
       14. The integrated circuit of  claim 13 , the specified percentage of the length x comprising approximately 75%. 
     
     
       15. The integrated circuit of  claim 12 , the reference voltage generator comprising: 
       a first p-type, thick-gate transistor having a source coupled to the external power supply, a gate, and a drain coupled to the gate;  
       a second p-type, thick-gate transistor having a source coupled to the drain of the first p-type transistor, a gate, and a drain coupled to the gate;  
       a third p-type, thick-gate transistor having a source coupled to the drain of the second p-type transistor, a gate operable to receive a mode indicator, and a drain coupled to ground;  
       a fourth p-type, thick-gate transistor having a source coupled to the drain of the second p-type transistor and a gate operable to receive an inverted mode indicator;  
       a fifth p-type, thin-gate transistor having a source coupled to a drain for the fourth p-type transistor, a gate coupled to ground, and a drain coupled to ground, the fifth p-type transistor comprising a length x, the third p-type transistor comprising a first specified multiple of the length x, and the fourth p-type transistor comprising a second specified multiple of the length x;  
       a charge assist circuit coupled to the drain of the first p-type transistor;  
       a capacitor coupled to the drain of the first p-type transistor; and  
       wherein the reference voltage generator is operable to generate the reference voltage at the drain of the first p-type transistor.  
     
     
       16. The integrated circuit of  claim 15 , the first specified multiple of the length x comprising approximately two and the is second specified multiple of the length x comprising approximately three. 
     
     
       17. The integrated circuit of  claim 11 , the level shifter further comprising an output inverter coupled to the drain of the first n-type transistor for the first circuit branch, the output inverter operable to receive a signal from the drain of the first n-type transistor for the first circuit branch and to invert the signal to generate external data in the external voltage domain. 
     
     
       18. The integrated circuit of  claim 17 , the output inverter comprising: 
       a p-type, thick-gate transistor having a source coupled to the external power supply and a gate coupled to the drain of the first n-type transistor for the first circuit branch;  
       an n-type, thick-gate transistor having a drain coupled to a drain for the p-type transistor, a source coupled to ground, and a gate coupled to the drain of the first n-type transistor for the first circuit branch; and  
       wherein the output inverter is operable to generate the external data at the drains of the p-type and n-type transistors.  
     
     
       19. The integrated circuit of  claim 11 , the input inverter comprising: 
       a p-type, thin-gate transistor having a source coupled to the internal power supply and a gate operable to receive the internal data;  
       an n-type, thin-gate transistor having a drain coupled to a drain for the p-type transistor, a source coupled to ground, and a gate operable to receive the internal data; and  
       wherein the input inverter is operable to generate the inverted internal data at the drains of the p-type and n-type transistors.  
     
     
       20. The integrated circuit of  claim 11 , the internal voltage domain comprising a swing voltage of less than 1.0 volt, the external voltage domain comprising a swing voltage of at least 3.0 volts, and the reference voltage comprising about 1.6 to about 2.2 volts.