Transistor with minimal hot electron injection

Abstract

A device comprising: a layer of gate oxide on a surface of the semiconductor substrate; a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side; a p-well implanted within a semiconductor substrate under the gate electrode; an n-well implanted in the p-well on the drain side; an n+ source region in the p-well outside of the n-well; an n+ drain region within the substrate inside the n-well; and lightly doped regions extending respectively from the source and drain regions toward the gate electrode.

What is claimed is:  
     
       1. A device comprising: 
       a layer of gate oxide on a surface of the semiconductor substrate;  
       a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side;  
       a p-well implanted within a semiconductor substrate under the gate electrode;  
       an n-well implanted in the p-well on the drain side;  
       an n+ source region in the p-well outside of the n-well; and  
       an n+ drain region within the substrate inside the n-well.  
     
     
       2. The device of  claim 1 , wherein the n-well extends slightly under the gate electrode. 
     
     
       3. The device of  claim 1 , further comprising digital circuitry positioned adjacent the device. 
     
     
       4. The device of  claim 1 , wherein the p-well is deeper than the n-well. 
     
     
       5. The device of  claim 1 , further comprising a second device, comprising: 
       a second gate electrode formed on the surface of the gate oxide;  
       a second n-well implanted within a semiconductor substrate under the second gate electrode;  
       a p+ source region in the second n-well; and  
       a p+ drain region within the substrate inside the second n-well.  
     
     
       6. The device of  claim 5 , wherein the second n-well is adjacent the p-well. 
     
     
       7. The device of  claim 1 , wherein the first and second n-wells are formed at the same time. 
     
     
       8. The device of  claim 1 , wherein the device is used in a digital circuit adjacent to a CMOS imaging element. 
     
     
       9. The device of  claim 1 , wherein the device is used in a digital circuit adjacent to a data converter. 
     
     
       10. The device of  claim 1 , wherein the device is used in a digital circuit adjacent to a radio frequency circuit.