Scalable stack-type DRAM memory structure and its manufacturing methods

Abstract

The scalable stack-type DRAM memory structure of the present invention comprises a scalable DRAM transistor structure and a scalable DRAM capacitor structure. The scalable DRAM transistor structure comprises a plurality of transistor-stacks, a plurality of common-drain regions, and a plurality of source regions being formed over a shallow-trench-isolation structure without a dummy-transistor structure by using a spacer-formation technique. The scalable DRAM capacitor structure comprises a plurality of rectangular tube-shaped cavities being formed over thin fourth conductive islands to form a high-capacity DRAM capacitor for each of DRAM cells; and a plurality of planarized conductive contact-islands over planarized third conductive islands being patterned and simultaneously etched with a plurality of bit-lines for forming a contactless DRAM memory. The cell size of a DRAM cell is scalable and can be made to be smaller than 6F 2 .

What is claimed is:  
     
       1. A scalable DRAM transistor structure comprising: 
       a semiconductor substrate of a first conductivity type;  
       a shallow-trench-isolation (STI) structure having an active region sandwiched by two parallel STI regions being formed on said semiconductor substrate;  
       a transistor-stack being formed transversely across a portion of said active region and said two parallel STI regions, wherein said transistor-stack comprises a masking sidewall dielectric spacer over a capping-dielectric layer being formed on an elongated second conductive layer with said elongated second conductive layer formed on a first conductive layer over a gate-dielectric layer in said active region and over two first raised field-oxide layers in said two parallel STI regions;  
       a common-drain region being located in one side portion of said transistor-stack comprising: a composite first sidewall dielectric spacer being formed over one sidewall of said transistor-stack and on a portion of a second flat bed being formed by two third raised field-oxide layers in said two parallel STI regions and a common-drain diffusion region of a second conductivity type in said active region, and a planarized third conductive island being formed on said common-drain diffusion region outside of said composite first sidewall dielectric spacer and between two second planarized dielectric layers being formed over said two third raised field-oxide layers in said two parallel STI regions;  
       a common-source region being located in another side portion of said transistor-stack comprising: two source regions and one isolation region being located between said two source regions, wherein said isolation region comprises a self-aligned shallow trench being formed in said semiconductor substrate of said active region to electrically isolate said two source regions with a first planarized dielectric layer being formed over said self-aligned shallow trench in said active region and on said two third raised field-oxide layers in said two parallel STI regions; and  
       said source region being formed near said transistor-stack comprising:  
       a composite second sidewall dielectric spacer being formed over another sidewall of said transistor-stack and on a portion of a first flat bed being formed by a source diffusion region of said second conductivity type in said active region and said two third raised field-oxide layers in said two parallel STI regions, a thin fourth conductive island being formed on said source diffusion region between said composite second sidewall dielectric spacer and said first planarized dielectric layer, and a third sidewall dielectric-spacer island being formed on said thin fourth conductive island in said active region and between said two second planarized dielectric layers in said two parallel STI regions.  
     
     
       2. The scalable DRAM transistor structure according to  claim 1 , wherein said composite first/second sidewall dielectric spacer being made of silicon-nitride comprises a first/second buffer-dielectric layer for forming a lightly-doped common-drain/source diffusion region of said second conductivity type and a first/second sidewall dielectric spacer being formed over one/another sidewall of said first/second buffer-dielectric layer for forming a shallow heavily-doped common-drain/source diffusion region of said second conductivity type within said lightly-doped common-drain/source diffusion region. 
     
     
       3. The scalable DRAM transistor structure according to  claim 1 , wherein said masking sidewall dielectric spacer being made of silicon-nitride is used as a hard mask to pattern said transistor-stack and to simultaneously define said common-drain region. 
     
     
       4. The scalable DRAM transistor structure according to  claim 1 , wherein said first planarized dielectric layer and said second planarized dielectric layer are preferably made of silicon-oxynitride or silicon-oxide. 
     
     
       5. The scalable DRAM transistor structure according to  claim 1 , wherein said third sidewall dielectric-spacer island being preferably made of doped oxide is formed by patterning a third sidewall dielectric spacer and said third sidewall dielectric spacer is used as a hard mask to simultaneously define said self-aligned shallow trench and said source region for forming said first planarized dielectric layer and said thin fourth conductive island, and can be selectively removed to form a rectangular tube-shaped cavity over said thin fourth conductive island for forming a scalable DRAM capacitor structure. 
     
     
       6. The scalable DRAM transistor structure according to  claim 5 , wherein said scalable DRAM capacitor structure comprises: 
       said rectangular tube-shaped cavity having a first-side formed by said composite second sidewall dielectric spacer, a second side formed by said first planarized dielectric layer, and a third-side and a fourth-side formed separately by said second planarized dielectric layer;  
       a sidewall fifth conductive layer being formed over an inner sidewall of said rectangular tube-shaped cavity together with said thin fourth conductive island to act as a source plate;  
       a capacitor-dielectric layer of a high dielectric-constant being at least formed over said sidewall fifth conductive layer and said thin fourth conductive island;  
       a planarized sixth conductive layer or a sixth conductive layer being formed over said capacitor-dielectric layer and patterned to act as a capacitor plate;  
       a planarized conductive contact-plug or a planarized conductive contact-island being formed on said planarized third conductive island to act as a bit-line node; and  
       a metal layer being patterned to be aligned above said active region and connected with said planarized conductive contact-plug or said planarized conductive contact-island to act as a bit line.  
     
     
       7. The scalable DRAM transistor structure according to  claim 5 , wherein said scalable DRAM capacitor structure comprises: 
       said rectangular tube-shaped cavity having a first-side formed by said composite second sidewall dielectric spacer and a first interlayer island being at least formed on a portion of said transistor-stack in said active region, a second side formed by a third planarized dielectric layer being formed on said first planarized dielectric layer, and a third side and a fourth-side formed separately by a fourth planarized dielectric layer on said second planarized dielectric layer;  
       a sidewall fifth conductive layer being at least formed over an inner sidewall of said rectangular tube-shaped cavity together with said thin fourth conductive island to act as a source plate;  
       a capacitor-dielectric layer being at least formed over said thin fourth conductive island and said sidewall fifth conductive layer;  
       a sixth conductive layer or a planarized sixth conductive layer being formed over said capacitor-dielectric layer and patterned to act as a capacitor plate;  
       a planarized conductive contact-plug or a planarized conductive contact-island being formed on said planarized third conductive island to act as a bit-line node; and  
       a metal layer being patterned to be aligned above said active region and connected with said planarized conductive contact-plug or said planarized conductive contact-island to act as a bit line.  
     
     
       8. The scalable DRAM transistor structure according to  claim 7 , wherein said first interlayer island comprises a first interlayer-conductive island on a first interlayer-dielectric island, a first interlayer-conductive island, a first interlayer-dielectric island, or a composite interlayer-dielectric island. 
     
     
       9. The scalable DRAM transistor structure according to  claim 7 , wherein said third planarized dielectric layer and said fourth planarized dielectric layer are preferably made of silicon-nitride or silicon-oxynitride. 
     
     
       10. A scalable DRAM memory structure comprising: 
       a scalable DRAM transistor structure being formed over a shallow-trench-isolation (STI) structure having an active region isolated by two parallel STI regions formed on a semiconductor substrate of a first conductivity type, wherein a transistor-stack comprising an elongated second conductive layer having a masking sidewall dielectric spacer over a capping-dielectric layer formed thereon is formed over a flat surface being formed by a first conductive layer over a gate-dielectric layer in said active region and over two first raised field-oxide layers in said two parallel STI regions; a common-drain region being located in one side portion of said transistor-stack comprises: a composite first sidewall dielectric spacer being formed over one sidewall of said transistor-stack and on a portion of a second flat bed being formed by two third raised field-oxide layers in said two parallel STI regions and a common-drain diffusion region of a second conductivity type in said active region, and a planarized third conductive island being formed on said common-drain diffusion region outside of said composite first sidewall dielectric spacer and between two second planarized dielectric layers being formed over said two third raised field-oxide layers in said two parallel STI regions; and a source region being located in another side portion of said transistor-stack comprises: a composite second sidewall dielectric spacer being formed over another sidewall of said transistor-stack and on a portion of a first flat bed being formed by a source diffusion region of said second conductivity type in said active region and said two third raised field-oxide layers in said two parallel STI regions, a thin fourth conductive island being formed on said source diffusion region between said composite second sidewall dielectric spacer and a first planarized dielectric layer, and a third sidewall dielectric-spacer island being formed on said thin fourth conductive island in said active region and between said two second planarized dielectric layers in said two parallel STI regions;  
       a rectangular tube-shaped cavity being formed over said thin fourth conductive island;  
       a sidewall fifth conductive layer being at least formed over an inner sidewall of said rectangular tube-shaped cavity together with said thin fourth conductive island to act as a source plate;  
       a capacitor-dielectric layer being at least formed over said thin fourth conductive island and said sidewall fifth conductive layer;  
       a planarized sixth conductive layer or a sixth conductive layer being formed over said capacitor-dielectric layer and patterned to act as a capacitor plate;  
       a planarized conductive contact-plug or a planarized conductive contact-island being formed on said planarized third conductive island to act as a bit-line node; and  
       a metal layer being patterned to be aligned above said active region and connected with said planarized conductive contact-plug or said planarized conductive contact-island to act as a bit line.  
     
     
       11. The scalable DRAM memory structure according to  claim 10 , wherein said rectangular tube-shaped cavity comprises: 
       first side being formed by said composite second sidewall dielectric spacer;  
       a second side being formed by said first planarized dielectric layer; and  
       a third side and a fourth side being separately formed by said second planarized dielectric layer.  
     
     
       12. The scalable DRAM memory structure according to  claim 10 , wherein said rectangular tube-shaped cavity comprises: 
       a first side being formed by said composite second sidewall dielectric spacer and a first interlayer island being at least formed on a portion of said transistor-stack in said active region;  
       a second side being formed by said third planarized dielectric layer formed on said first planarized dielectric layer; and  
       a third side and a fourth side being separately formed by said fourth planarized dielectric layer formed on said second planarized dielectric layer.  
     
     
       13. The sealable DRAM memory structure according to  claim 12 , wherein said first interlayer island comprises a first interlayer-conductive island on a first interlayer-dielectric island, a first interlayer-dielectric island, a first interlayer-conductive island, or a composite interlayer-dielectric island. 
     
     
       14. The scalable DRAM memory structure according to  claim 10 , wherein said masking sidewall dielectric spacer being preferably made of silicon-nitride is used as a hard mask to pattern said transistor-stack and to simultaneously define said common-drain region. 
     
     
       15. The scalable DRAM memory structure according to  claim 10 , wherein said composite first/second sidewall dielectric spacer being preferably made of silicon-nitride comprises a first/second buffer-dielectric layer for forming a lightly-doped common-drain/source diffusion region of said second conductivity type and a first/second sidewall dielectric spacer being formed over one/another sidewall of said first/second buffer-dielectric layer for forming a shallow heavily-doped common-drain/source diffusion region of said second conductivity type within said lightly-doped common-drain/source diffusion region. 
     
     
       16. The scalable DRAM memory structure according to  claim 10 , wherein said third sidewall dielectric-spacer island being preferably made of doped oxide is formed by patterning a third side wall dielectric spacer and said third sidewall dielectric spacer is used as a hard mask to simultaneously define said self-aligned shallow trench and said source region for forming said first planarized dielectric layer and said thin fourth conductive island.