EEPROM memory cell array architecture for substantially eliminating leakage current

Abstract

An EEPROM memory cell array architecture (50) that substantially eliminates leakage current to allow for reading memory cells (20) in a memory cell array of, for example, a CPLD at lower voltages than are possible with prior art architectures, thereby facilitating development of low voltage applications. This is accomplished by associating each wordline of the memory cell array with a ground transistor (26). On one embodiment, the ground transistor (26) can be a high voltage transistor, in which case the same high voltage control signal can control both the ground transistor (26) and the memory cell=s read transistor (32). In another embodiment, the ground transistor (26) is a low voltage transistor controlled by a separate low voltage control signal.

What is claimed is:  
     
       1. A memory array architecture comprising: 
       a memory cell having a read node, an access node, and a ground node, wherein the memory cell is associated with both a bitline and a wordline;  
       a sense amplifier associated with the bitline;  
       a ground transistor associated with the wordline;  
       a first connection connecting the read node of the memory cell associated with the bitline to the sense amplifier;  
       a second connection connecting the access node of the memory cell of the wordline to a first terminal of the ground transistor; and  
       a third connection connecting the ground node of the memory cell of the wordline to a second terminal of the ground transistor.  
     
     
       2. The memory array architecture as set forth in  claim 1 , wherein the memory cell is an electrically erasable programmable read-only memory. 
     
     
       3. The memory array architecture as set forth in  claim 1 , wherein the ground transistor is a high voltage NMOS transistor. 
     
     
       4. The memory array architecture as set forth in  claim 1 , wherein the memory cell further includes a read transistor connected to the access node, and the read transistor and the ground transistor are both controlled by a single control signal propagated on the second connection. 
     
     
       5. The memory array architecture as set forth in  claim 4 , wherein the read transistor has a threshold voltage which is lower than approximately 0.8V. 
     
     
       6. A memory array architecture comprising: 
       a memory cell having a read node, an access node, a ground node, and a read transistor connected to the access node and having a threshold voltage which is lower than approximately 0.8V, wherein the memory cell is associated with both a bitline and a wordline;  
       a sense amplifier associated with the bitline;  
       a high voltage ground transistor associated with the wordline;  
       a first connection connecting the read node of the memory cell of the bitline to the sense amplifier;  
       a second connection connecting the access node of the memory cell of the wordline to a first terminal of the ground transistor; and  
       a third connection connecting the ground node of the memory cell of the wordline to a second terminal of the ground transistor, wherein the read transistor and the ground transistor are both controlled by a single control signal propagated on the second connection.  
     
     
       7. The memory array architecture as set forth in  claim 6 , wherein the memory cell is an electrically erasable programmable read-only memory. 
     
     
       8. A memory array architecture comprising: 
       a memory cell having a read node and a ground node, wherein the memory cell is associated with both a bitline and a wordline;  
       a sense amplifier associated with the bitline;  
       a ground transistor associated with the wordline;  
       a first connection connecting the read node of the memory cell associated with the bitline to the sense amplifier;  
       a second connection connected to a first terminal of the ground transistor and adapted to propagate a low voltage control signal thereto; and  
       a third connection connecting the ground node of the memory cell of the wordline to a second terminal of the ground transistor.  
     
     
       9. The memory array architecture as set forth in  claim 8 , wherein the memory cell is an electrically erasable, programmable read-only memory. 
     
     
       10. The memory array architecture as set forth in  claim 8 , wherein the ground transistor is a low voltage NMOS transistor controlled by a low voltage control signal. 
     
     
       11. The memory array architecture as set forth in  claim 8 , wherein the memory cell further includes a read transistor connected to the access node, and the read transistor is controlled by a high voltage control signal. 
     
     
       12. The memory array architecture as set forth in  claim 11 , wherein the read transistor has a threshold voltage which is lower than approximately 0.8V. 
     
     
       13. A memory array architecture comprising: 
       a memory cell having a read node, an access node, a ground node, and a read transistor connected to the access node and having a threshold voltage which is lower than approximately 0.8V, wherein the memory cell is associated with both a bitline and a wordline;  
       a sense amplifier associated with the bitline;  
       a low voltage ground transistor associated with the wordline;  
       a first connection connecting the read node of the memory cell of the bitline to the sense amplifier;  
       a second connection connected to the read transistor via the access node and adapted to propagate a high voltage control signal thereto;  
       a third connection connected to a first terminal of the ground transistor and adapted to propagate a low voltage control signal thereto; and  
       a fourth connection connecting the ground node of the memory cell of the wordline to a second terminal of the ground transistor.  
     
     
       14. The memory array architecture as set forth in  claim 13 , wherein the memory cell is an electrically erasable programmable read-only memory. 
     
     
       15. A method of implementing memory array circuitry, wherein the memory array circuitry includes a memory cell having a read node, an access node, a ground node, and a read transistor connected to the access node, and wherein the memory cell is associated with both a bitline and a wordline, the method comprising the steps of: 
       (a) connecting with a first connection the read node of the memory cell of the bitline to a sense amplifier;  
       (b) connecting with a second connection the access node of the memory cell of the wordline to a first terminal of a ground transistor;  
       (d) connecting with a third connection the ground node of the memory cell of the wordline to a second terminal of the ground transistor; and  
       (d) controlling the read transistor and the ground transistor with a single control signal propagated on the second connection.  
     
     
       16. The method of  claim 15 , wherein the memory cell is an electrically erasable programmable read-only memory. 
     
     
       17. The method of  claim 15 , wherein the ground transistor is a high voltage NMOS transistor. 
     
     
       18. The method of  claim 15 , wherein the read transistor has a threshold voltage which is lower than approximately 0.8V. 
     
     
       19. A method of implementing memory array circuitry, wherein the memory array circuitry includes a memory cell having a read node, an access node, a ground node, and a read transistor connected to the access node, and wherein the memory cell is associated with both a bitline and a wordline, the method comprising the steps of: 
       (a) connecting the read node of the memory cell of the bitline to a sense amplifier with a first connection;  
       (b) controlling the read transistor of the memory cell of the wordline with a high voltage control signal;  
       (c) connecting the ground node of the memory cell of the wordline to a terminal of the ground transistor with a second connection; and  
       (d) controlling the ground transistor with a low voltage control signal.  
     
     
       20. The method of  claim 19 , wherein the memory cell is an electrically erasable programmable read-only memory. 
     
     
       21. The method of  claim 19 , wherein the ground transistor is a low voltage NMOS transistor. 
     
     
       22. The method of  claim 19 , wherein the read transistor has a threshold voltage which is lower than approximately 0.8V.