High speed random number generation

Abstract

A high-speed random number generator (1) comprising a physical random number generator, having a data input, an output and a pseudo-random generator coupled to the output of the physical random generator. The pseudo-random generator has an input adapted to receive a germ delivered by the physical generator and deliver at an output a pseudo-random output signal. The physical generator comprises a logic circuit that includes at least a data input (D) and a clock input (CLK), the data input (D) receiving a first "high frequency" clock signal H1 and the clock input (CLK) receiving a second "low frequency" clock signal H2, with the "high frequency" signal H1 being sampled by the "low frequency" signal H2. The two clock signals H1 and H2 are of different frequencies respectively and issue from two different first (OSC1 and OSC2) operating asynchronously from one another and not adhering to the setup time of the logic circuit (10). The logic circuit is arranged to deliver at an output a signal in an intermediate state qualified as metastable between "0" and "1" and being constituted by a random number sequence. The metastability of the signal obtained as an output from the logic circuit (10) is accentuated by phase noise of the first oscillator (OSC1) generating the "high frequency" signal H1. The pseudo-random generator is arranged to re-inject part of the pseudo-random output signal into the physical generator. An internal memory stores the random numbers obtained as output signals from the pseudo-random generator. The two generators run on the same second "high frequency" clock H generated by the external oscillator (7).

What is claimed is:  
     
       1. High-speed random number generator ( 1 ) comprising a physical random number generator ( 5 ), having a data input and an output, and a pseudo-random generator ( 6 ) coupled to the output of the physical random generator ( 5 ), said pseudo-random generator having an input adapted to receive a germ delivered by the physical generator and an output from which is delivered a pseudo-random output signal, said physical generator ( 5 ) comprising a logic circuit ( 10 ) having a set up time and at least a data input (D) and a clock input (CLK), the data input (D) adapted to receive a first “high frequency” clock signal H 1  and the clock input (CLK) adapted to receive a second “low frequency” clock signal H 2 , the “high frequency” signal H 1  adapted to be sampled by the “low frequency” signal H 2 , the two clock signals H 1  and H 2  being of different frequencies, respectively, and issuing from two different first (OSC 1 ) and second (OSC 2 ) oscillators operating asynchronously from one another and not adhering to the setup time of the logic circuit ( 10 ), the logic circuit ( 10 ) arranged to deliver at an output thereof a signal in an intermediate state qualified as metastable between “0” and “1” and being constituted by a random number sequence, the metastability of the signal obtained as an output from the logic circuit ( 10 ) being accentuated by phase noise of the first oscillator (OSC 1 ) generating the “high frequency” signal H 1 , the pseudo-random generator ( 6 ) being arranged to re-inject part of the pseudo-random output signal into the physical generator ( 5 ) and an internal memory ( 9 ) for storing random numbers obtained as output signals from the pseudo-random generator ( 6 ) and an external oscillator having a “high frequency” clock signal output (H), the physical random number generator ( 5 ) and the pseudo-random number generator ( 6 ) running on the same second “high frequency” clock signal H generated by the external oscillator ( 7 ). 
     
     
       2. A random number generator according to  claim 1 , characterized in that the physical generator ( 5 ) includes a counter ( 11 ) which, from the “high frequency” clock signal H generated by the external oscillator ( 7 ), generates the “low frequency” clock signal H 2 , which samples the input signal of the physical generator ( 5 ). 
     
     
       3. A random number generator according to  claim 2 , characterized in that part of the signal output from the pseudo-random generator is re-injected into the counter ( 11 ) that generates the “low frequency” signal, in order to force the variability of the period of the “low frequency” signal. 
     
     
       4. A random number generator according to  claim 3 , characterized in that the physical generator ( 5 ) includes a shift register ( 13 ) having a data input arranged to receive a signal output from the latch-type logic circuit ( 10 ), and a clock input (CLK) arranged to receive the “low frequency” signal H 2  generated by the counter ( 11 ), the shift register ( 13 ) delivering through its output the germ that feeds the pseudo-random generator ( 6 ). 
     
     
       5. A random number generator according to  claim 4 , characterized in that the physical generator ( 5 ) also includes an “exclusive OR” logic gate ( 12 ), coupled between the latch-type logic circuit ( 10 ) and the shift register ( 13 ), and receiving in a first input the signal output from the logic circuit ( 10 ), and in a second input a bit of the signal output from the pseudo-random generator ( 6 ), in order to compensate for a possible failure of the physical generator ( 5 ). 
     
     
       6. A random number generator according to  claim 5 , characterized in that the physical generator ( 5 ) includes a counter ( 14 ) that receives in its input the “low frequency” clock signal H 2 , and whose output signal controls the renewal rate of the germ in the pseudo-random generator ( 6 ). 
     
     
       7. A random number generator according to  claim 6 , characterized in that it also includes a test module ( 15 ) coupled to the input of the physical generator ( 5 ) that receives the “high frequency” signals H and H 1  as an output and delivers as an output an error signal upon malfunction of the first oscillator delivering the “high frequency” signal H 1 , to invalidate the output of the physical generator ( 5 ) by forcing the writing of zeros into an internal memory ( 9 ). 
     
     
       8. A random number generator according to  claim 5 , characterized in that it also includes a test module ( 15 ) coupled to the input of the physical generator ( 5 ) that receives the “high frequency” signals H and H 1  as an output and delivers as an output an error signal upon malfunction of the first oscillator delivering the “high frequency” signal H 1 , to invalidate the output of the physical generator ( 5 ) by forcing the writing of zeros into an internal memory ( 9 ). 
     
     
       9. A random number generator according to  claim 4 , characterized in that it also includes a test module ( 15 ) coupled to the input of the physical generator ( 5 ) that receives the “high frequency” signals H and H 1  as an output and delivers as an output an error signal upon malfunction of the first oscillator delivering the “high frequency” signal H 1 , to invalidate the output of the physical generator ( 5 ) by forcing the writing of zeros into an internal memory ( 9 ). 
     
     
       10. A random number generator according to  claim 3 , characterized in that it also includes a test module ( 15 ) coupled to the input of the physical generator ( 5 ) that receives the “high frequency” signals H and H 1  as an output and delivers as an output an error signal upon malfunction of the first oscillator delivering the “high frequency” signal H 1 , to invalidate the output of the physical generator ( 5 ) by forcing the writing of zeros into an internal memory ( 9 ). 
     
     
       11. A random number generator according to  claim 2 , characterized in that it also includes a test module ( 15 ) coupled to the input of the physical generator ( 5 ) that receives the “high frequency” signals H and H 1  as an output and delivers as an output an error signal upon malfunction of the first oscillator delivering the “high frequency” signal H 1 , to invalidate the output of the physical generator ( 5 ) by forcing the writing of zeros into an internal memory ( 9 ). 
     
     
       12. A random number generator according to  claim 2 , characterized in that it comprises in its entirety an FPGA component. 
     
     
       13. A random number generator according to  claim 1 , characterized in that it also includes a test module ( 15 ) coupled to the input of the physical generator ( 5 ) that receives the “high frequency” signals H and H 1  as an output and delivers as an output an error signal upon malfunction of the first oscillator delivering the “high frequency” signal H 1 , to invalidate the output of the physical generator ( 5 ) by forcing the writing of zeros into an internal memory ( 9 ). 
     
     
       14. A random number generator according to  claim 1 , characterized in that the pseudo-random generator ( 6 ) implements an algorithm of the multiply-with-carry type. 
     
     
       15. A mechanism for generating random numbers on demand, having a physical random number generator ( 5 ), having a data input and an output, and a pseudo-random generator ( 6 ) coupled to the output of the physical random generator ( 5 ), said pseudo-random generator having an input adapted to receive a germ delivered by the physical generator and an output from which is delivered a pseudo-random output signal, said physical generator ( 5 ) comprising a logic circuit ( 10 ) having a set up time and at least a data input (D) and a clock input (CLK), the data input (D) adapted to receive a first “high frequency” clock signal H 1  and the clock input (CLK) adapted to receive a second “low frequency” clock signal H 2 , the “high frequency” signal H 1  adapted to be sampled by the “low frequency” signal H 2 , the two clock signals H 1  and H 2  being of different frequencies respectively and issuing from two different first (OSC 1 ) and second (OSC 2 ) oscillators operating asynchronously from one another and not adhering to the setup time of the logic circuit ( 10 ), the logic circuit ( 10 ) arranged to deliver at an output thereof a signal in an intermediate state qualified as metastable between “0” and “1” and being constituted by a random number sequence, the metastability of the signal obtained as an output from the logic circuit (1.0) being accentuated by phase noise of the first oscillator (OSC 1 ) generating the “high frequency” signal H 1 , the pseudo-random generator ( 6 ) being arranged to re-inject part of the pseudo-random output signal into the physical generator ( 5 ) and an internal memory ( 9 ) for storing random numbers obtained as output signals from the pseudo-random generator ( 6 ) and an external oscillator having a “high frequency” clock signal output (H), the physical random number generator ( 5 ) and the pseudo-random number generator ( 6 ) running on the same second “high frequency” clock signal H generated by the external oscillator ( 7 ), comprising a random number generator ( 1 ) and further including a dual-port memory ( 3 ) including a receiving buffer ( 3   1 ), coupled to the output of the generator ( 1 ) via a bus, and a microprocessor ( 2 ) coupled to the dual-port memory ( 3 ) via a microprocessor bus, communicating with the generator ( 1 ) via the dual-port memory ( 3 ) and posting in the dual-port memory ( 3 ) a command word comprising an address and a count containing a maximum number of random words to be stored, and the receiving buffer ( 3   1 ) of the dual-port memory ( 3 ), at the request of the microprocessor ( 2 ), arranged to be fed by the internal memory ( 9 ) of the generator ( 1 ) until a count corresponding to a given maximum number of random numbers has elapsed, then utilized by the microprocessor ( 2 ). 
     
     
       16. A mechanism according to  claim 15 , characterized in that the physical generator ( 5 ) includes a block ( 11 ) which, from the “high frequency” clock signal H generated by the external oscillator ( 7 ), generates the “low frequency” clock signal H 2 , which samples the input signal of the physical generator ( 5 ). 
     
     
       17. A mechanism according to  claim 15 , characterized in that part of the signal output from the pseudo-random generator is re-injected into the counter ( 11 ) that generates the “low frequency” signal, in order to force the variability of the period of the “low frequency” signal. 
     
     
       18. A mechanism according to  claim 15 , characterized in that the physical generator ( 5 ) includes a shift register ( 13 ) having a data input arranged to receive a signal output from the latch-type logic circuit ( 10 ), and a clock input (CLK) arranged to receive the “low frequency” signal H 2  generated by the counter ( 11 ), the shift register ( 13 ) delivering through its output the germ that feeds the pseudo-random generator ( 6 ). 
     
     
       19. A mechanism according to  claim 15 , characterized in that the physical generator ( 5 ) also includes an “exclusive OR” logic gate ( 12 ), coupled between the latch-type logic circuit ( 10 ) and the shift register ( 13 ), and receiving in a first input the signal output from the logic circuit ( 10 ), and in a second input a bit of the signal output from the pseudo-random generator ( 6 ), in order to compensate for a possible failure of the physical generator ( 5 ). 
     
     
       20. A mechanism according to  claim 15 , characterized in that the physical generator ( 5 ) includes a counter ( 14 ) that receives in its input the “low frequency” clock signal H 2 , and whose output signal controls the renewal rate of the germ in the pseudo-random generator ( 6 ). 
     
     
       21. A card for accelerating the cryptographic functions of a computing machine, characterized in that it supports a random generator ( 1 ) comprising a physical random number generator ( 5 ), having a data input and an output, and a pseudo-random generator ( 6 ) coupled to the output of the physical random generator ( 5 ), said pseudo-random generator having an input adapted to receive a germ delivered by the physical generator and an output from which is delivered a pseudo-random output signal, said physical generator ( 5 ) comprising a logic circuit ( 10 ) having a set up time and at least a data input (D) and a clock input (CLK), the data input (D) adapted to receive a first “high frequency” clock signal H 1  and the clock input (CLK) adapted to receive a second “low frequency” clock signal H 2 , the “high frequency” signal H 1  adapted to be sampled by the “low frequency” signal H 2 , the two clock signals H 1  and H 2  being of different frequencies, respectively, and issuing from two different first (OSC 1 ) and second (OSC 2 ) oscillators operating asynchronously from one another and not adhering to the setup time of the logic circuit ( 10 ), the logic circuit ( 10 ) arranged to deliver at an output thereof a signal in an intermediate state qualified as metastable between “0” and “1” and being constituted by a random number sequence, the metastability of the signal obtained as an output from the logic circuit (1.0) being accentuated by phase noise of the first oscillator (OSC 1 ) generating the “high frequency” signal H 1 , the pseudo-random generator ( 6 ) being arranged to re-inject part of the pseudo-random output signal into the physical generator ( 5 ) and an internal memory ( 9 ) for storing random numbers obtained as output signals from the pseudo-random generator ( 6 ) and an external oscillator having a “high frequency” clock signal output (H), the physical random number generator ( 5 ) and the pseudo-random number generator ( 6 ) running on the same second “high frequency” clock signal H generated by the external oscillator ( 7 ). 
     
     
       22. A card according to  claim 21 , characterized in that the physical generator ( 5 ) includes a counter ( 11 ) which, from the “high frequency” clock signal H generated by the external oscillator ( 7 ), generates the “low frequency” clock signal H 2 , which samples the input signal of the physical generator ( 5 ). 
     
     
       23. A card according to  claim 21 , characterized in that part of the signal output from the pseudo-random generator is re-injected into the counter ( 11 ) that generates the “low frequency” signal, in order to force the variability of the period of the “low frequency” signal. 
     
     
       24. A card according to  claim 21 , characterized in that the physical generator ( 5 ) includes a shift register ( 13 ) having a data input arranged to receive a signal output from the latch-type logic circuit ( 10 ), and a clock input (CLK) arranged to receive the “low frequency” signal H 2  generated by the block ( 11 ), the shift register ( 13 ) delivering through its output the germ that feeds the pseudo-random generator ( 6 ). 
     
     
       25. A card according to  claim 21 , characterized in that the physical generator ( 5 ) also includes an “exclusive OR” logic gate ( 12 ), coupled between the latch-type logic circuit ( 10 ) and the shift register ( 13 ), and receiving in a first input the signal output from the logic circuit ( 10 ), and in a second input a bit of the signal output from the pseudo-random generator ( 6 ), in order to compensate for a possible failure of the physical generator ( 5 ). 
     
     
       26. A card according to  claim 21 , characterized in that the physical generator ( 5 ) includes a counter ( 14 ) that receives in its input the “low frequency” clock signal H 2 , and whose output signal controls the renewal rate of the germ in the pseudo-random generator ( 6 ). 
     
     
       27. A card for accelerating the cryptographic functions of a computing machine, characterized in that it supports a mechanism for generating random numbers on demand, having a physical random number generator ( 5 ), having a data input and an output, and a pseudo-random generator ( 6 ) coupled to the output of the physical random generator ( 5 ), said pseudo-random generator having an input adapted to receive a germ delivered by the physical generator and an output from which is delivered a pseudo-random output signal, said physical generator ( 5 ) comprising a logic circuit ( 10 ) having a set up time and at least a data input (D) and a clock input (CLK), the data input (D) adapted to receive a first “high frequency” clock signal H 1  and the clock input (CLK) adapted to receive a second “low frequency” clock signal H 2 , the “high frequency” signal H 1  adapted to be sampled by the “low frequency” signal H 2 , the two clock signals H 1  and H 2  being of different frequencies, respectively, and issuing from two different first (OSC 1 ) and second (OSC 2 ) oscillators operating asynchronously from one another and not adhering to the setup time of the logic circuit ( 10 ), the logic circuit ( 10 ) arranged to deliver at an output thereof a signal in an intermediate state qualified as metastable between “0” and “1” and being constituted by a random number sequence, the metastability of the signal obtained as an output from the logic circuit (1.0) being accentuated by phase noise of the first oscillator (OSC 1 ) generating the “high frequency” signal H 1 , the pseudo-random generator ( 6 ) being arranged to re-inject part of the pseudo-random output signal into the physical generator ( 5 ) and an internal memory ( 9 ) for storing random numbers obtained as output signals from the pseudo-random generator ( 6 ) and an external oscillator having a “high frequency” clock signal output (H), the physical random number generator ( 5 ) and the pseudo-random number generator ( 6 ) running on the same second “high frequency” clock signal H generated by the external oscillator ( 7 ), comprising a random number generator ( 1 ) and further including a dual-port memory ( 3 ) including a receiving buffer ( 3   1 ), coupled to the output of the generator ( 1 ) via a bus, and a microprocessor ( 2 ) coupled to the dual-port memory ( 3 ) via a microprocessor bus, communicating with the generator ( 1 ) via the dual-port memory ( 3 ) and posting in the dual-port memory ( 3 ) a command word comprising an address and a count containing a maximum number of random words to be stored, and the receiving buffer ( 3   1 ) of the dual-port memory ( 3 ), at the request of the microprocessor ( 2 ), arranged to be fed by the internal memory ( 9 ) of the generator ( 1 ) until a count corresponding to a given maximum number of random numbers has elapsed, then utilized by the microprocessor ( 2 ). 
     
     
       28. A card according to  claim 27 , characterized in that the physical generator ( 5 ) includes a counter ( 11 ) which, from the “high frequency” clock signal H generated by the external oscillator ( 7 ), generates the “low frequency” clock signal H 2 , which samples the input signal of the physical generator ( 5 ). 
     
     
       29. A card according to  claim 27 , characterized in that part of the signal output from the pseudo-random generator is re-injected into the counter ( 11 ) that generates the “low frequency” signal, in order to force the variability of the period of the “low frequency” signal. 
     
     
       30. A card according to  claim 27 , characterized in that the physical generator ( 5 ) includes a shift register ( 13 ) having a data input arranged to receive a signal output from the latch-type logic circuit ( 10 ), and a clock input (CLK) arranged to receive the “low frequency” signal H 2  generated by the block ( 11 ), the shift register ( 13 ) delivering through its output the germ that feeds the pseudo-random generator ( 6 ). 
     
     
       31. A card according to  claim 27 , characterized in that the physical generator ( 5 ) also includes an “exclusive OR” logic gate ( 12 ), coupled between the latch-type logic circuit ( 10 ) and the shift register ( 13 ), and receiving in a first input the signal output from the logic circuit ( 10 ), and in a second input a bit of the signal output from the pseudo-random generator ( 6 ), in order to compensate for a possible failure of the physical generator ( 5 ). 
     
     
       32. A card according to  claim 27 , characterized in that the physical generator ( 5 ) includes a counter ( 14 ) that receives in its input the “low frequency” clock signal H 2 , and whose output signal controls the renewal rate of the germ in the pseudo-random generator ( 6 ).