Time tracking loop for pilot aided direct sequence spread spectrum systems

Abstract

A novel design of, and method of operation for, a coherent delay lock loop (DLL) for communication systems that employ a pilot channel or pilot symbols is disclosed. Pilot information is used to produce an estimate of signal phase and thereby remove the need for the magnitude operation within the DLL arms. The disclosed design and method afford better time-tracking performance by avoiding the squaring loss (due to the magnitude operation) encountered in noncoherent DLL designs. Alternative embodiments disclose designs and methods that are robust to signal amplitude variation. A first alternative normalizes a DLL error signal by a computed estimate of the squared magnitude of the pilot signal. A second alternative normalizes the error signal using only the early and late signals and therefore is applicable for noncoherent DLL designs as well as coherent DLL designs.

What is claimed is:  
     
       1. A method of normalizing an error signal in a delay lock loop having an early-late structure, comprising the steps of: 
       subtracting a portion or a late signal from a portion of an early signal to form an error signal;  
       adding the real number part of the early signal to the real number part of the late signal, to generate a normalizing signal; and  
       dividing said error signal by said normalizing signal to generate a normalized error signal.  
     
     
       2. A delay lock loop comprising: 
       an on-time signal correlator that correlates an on-time signal with a PN code sequence, to produce a correlated on-time signal;  
       an on-time signal conjugator that conjugates said correlated on-time signal, to produce a conjugated on-time signal;  
       a plurality of delay lock loop arm signal multipliers, wherein each of said multipliers generates a real arm signal by removing phase components from an arm signal by multiplying said arm signal with said conjugated on-time signal;  
       a subtractor that generates an error signal proportional to the difference between said real arm signals generated by said multipliers;  
       an adder that generates a normalizing signal propoertional to the sum of said real arm signals; and  
       a divider that generates a normalized error signal by dividing said error signal by said normalizing signal.  
     
     
       3. The delay lock loop of  claim 2 , wherein said delay lock loop has an early-late structure. 
     
     
       4. The delay lock loop of  claim 2 , wherein said delay lock loop has an early-on time structure. 
     
     
       5. The delay lock loop of  claim 2 , wherein said delay lock loop has a tau-dithered structure. 
     
     
       6. The delay lock loop of  claim 2 , wherein said arm signal is an early signal. 
     
     
       7. The delay lock loop of  claim 2 , wherein said arm signal is a late signal. 
     
     
       8. A delay lock loop, comprising: 
       a plurality of arm signal nonlinear squaring circuits, wherein each of said squaring circuits generates a real arm signal by removing phase components from an arm signal of said delay lock loop by squaring said arm signal;  
       a subtractor that generates an error signal proportional to the difference between said real arm signals generated by said plurality of nonlinear squaring circuits;  
       an adder that generates a normalizing signal proportional to the sum of said real arm signals; and  
       a divider that generates a normalized error signal by dividing said error signal by said normalizing signal.  
     
     
       9. The delay lock loop of  claim 8 , wherein said delay lock loop has an early-late structure. 
     
     
       10. The delay lock loop of  claim 8 , wherein said delay lock loop has an early-on time structure. 
     
     
       11. The delay lock loop of  claim 8 , wherein said delay lock loop has a tau-dithered structure. 
     
     
       12. The delay lock loop of  claim 8 , wherein said arm signal is an early signal. 
     
     
       13. The delay lock loop of  claim 8 , wherein said arm signal is a late signal.