Power-on reset circuit

Abstract

A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.

What is claimed is:  
     
       1. A power-on reset (POR) circuit, comprising: 
       (a) a plurality of diode means for setting a temperature-independent time delay, said plurality of diode means being electrically coupled to a power supply voltage with at least one of said plurality of diode means having a low threshold voltage;  
       (b) a switching transistor means coupled to the plurality of diode means for setting the temperature independent time delay, the POR circuit having a trip point which depends solely on characteristics of said switching transistor means; and  
       (c) a buffer circuit electrically coupled to the switching transistor means.  
     
     
       2. The POR circuit of  claim 1 , wherein the means for setting-temperature independent time delay comprising a plurality of diode means electrically coupled in series to one another. 
     
     
       3. The POR of  claim 2 , wherein the plurality of diode means for setting the temperature independent time delay comprises: 
       a first n-channel MOS transistor (NMOS) connected as a diode having a gate electrically coupled to a drain and to a second terminal of the CMOS capacitor;  
       a second n-channel MOS transistor (NMOS) transistor connected as a diode having a gate electrically coupled to a drain and to a source of the first NMOS transistor; and a low-threshold n-channel MOS (NMOS) transistor connected as a diode with a gate electrically coupled to a drain and to a source of the second NMOS transistor.  
     
     
       4. The POR circuit of  claim 2 , wherein the plurality of diode means comprising a plurality of p-n junction diodes coupled together in series, each diode having an anode and a cathode; wherein the cathode of a first diode is coupled to power supply voltage and protecting the POR circuit from ESD and latch-up, and of the last p-n diode is coupled to the switching transistor means. 
     
     
       5. The POR circuit of  claim 1 , further comprises a means for coupling to the power supply voltage and for protecting the POR circuit against latch-up and ESD comprising: 
       a p-channel MOS (PMOS) transistor having a drain electrically coupled to the power supply voltage, a gate electrically coupled to an electrical ground.  
     
     
       6. The POR circuit of  claim 1 , wherein the switching transistor means is an n-channel MOS (NMOS) transistor having a source coupled to the electrical ground, a gate electrically coupled to a first terminal of a pull-down resistor, and a drain coupled to a first terminal of a pull-up resistor, wherein a second terminal of the pull-up resistor is coupled to the power supply voltage. 
     
     
       7. The POR circuit of  claim 1 , wherein the plurality of buffer circuits comprises a plurality of MOS inverters coupled in series to one another and an input terminal of a first CMOS inverter is electrically coupled to the drain of the transistor means and an output terminal of a last MOS inverter forms an output of the POR circuit. 
     
     
       8. The POR circuit of  claim 1 , wherein the buffer circuit comprises a first MOS inverter coupled in series to a second MOS inverter and a third MOS inverter. 
     
     
       9. The POR circuit of  claim 1 , wherein the buffer means further comprising: 
       a first pull-up MOS capacitor having a first terminal coupled to the power supply voltage and a second terminal coupled to the gate of the n-channel MOS transistor;  
       a first CMOS inverter having an input terminal coupled to the second terminal of the second p-channel MOS capacitor;  
       a first pull-down MOS capacitor having a first terminal coupled to the output of the first CMOS inverter and the second terminal coupled to the electrical ground;  
       a second CMOS inverter having an input terminal electrically coupled to the output terminal of the first CMOS inverter;  
       a second pull-up MOS capacitor having the first terminal electrically coupled to the output terminal of the second CMOS inverter and a second terminal coupled to the power supply voltage;  
       a third CMOS inverter having an input terminal electrically coupled to the output terminal of the second CMOS inverter;  
       a second pull-down MOS capacitor having a first terminal coupled to the electrical ground and a second terminal electrically coupled to the output terminal of the third CMOS inverter;  
       a fourth CMOS inverter having an input terminal coupled to the output terminal of the third CMOS inverter; and  
       a fifth CMOS inverter having an input terminal electrically coupled to the output terminal of the fourth terminal and an output terminal forms an output of the CMOS POR circuit.  
     
     
       10. A power-on reset circuit having a trip point, comprising: 
       a p-channel MOS (PMOS) transistor having a source electrically coupled to a power supply voltage, a gate electrically coupled to an electrical ground;  
       a first NMOS transistor connected as a diode having a gate electrically coupled to a drain and to a second terminal of a first CMOS capacitor;  
       a second NMOS transistor connected as a diode having a gate electrically coupled to a drain and to a source of the first NMOS transistor;  
       a low-threshold n-channel MOS (NMOS) transistor with a gate electrically coupled to a drain and to a source of the second NMOS transistor;  
       a pull-down resistor having a first terminal and a second terminal, the first terminal being electrically coupled to a source of the p-channel MOS transistor and the second terminal electrically coupled to an electrical ground so that the current flowing from the power supply voltage through the pull-down resistor is limited; and  
       a transistor switch having a source coupled to the electrical ground and a gate electrically coupled to the first terminal of the resistor detecting a rising edge of the power voltage supply, wherein the trip point of the POR circuit depends on the characteristics of the transistor switch;  
       a pull-up resistor having a first terminal and a second terminal, first terminal being electrically coupled to the power supply voltage and the second terminal is coupled to a drain of the CMOS switch; and a plurality of CMOS inverters coupled in series to one another and an input terminal of the a first CMOS inverter is electrically coupled to the second terminal of the pull-up resistor and an output terminal of a last CMOS inverter forms an output of the CMOS POR circuit.  
     
     
       11. A CMOS power-on reset (POR) circuit having a trip point, comprising: 
       a first p-channel MOS (PMOS) transistor having a source electrically coupled to a power supply voltage, a gate electrically coupled to an electrical ground;  
       a first n-channel MOS (NMOS) transistor connected as a diode with a drain electrically coupled to the source of the p-channel MOS transistor and a gate electrically coupled to the drain;  
       a pull-down resistor having a first terminal coupled to the source of the first NMOS transistor and a second terminal electrically coupled to the electrical ground so that current flowing from the power supply voltage to ground is limited;  
       an n-channel MOS (NMOS) transistor switch having a gate electrically coupled to the first terminal of the pull-down resistor and a source electrically coupled to the electrical ground;  
       a first pull-up n-channel MOS (NMOS) transistor having a drain electrically coupled to the power supply voltage, a gate coupled to the electrical ground and a source electrically coupled to the drain of the NMOS transistor, wherein the trip point of the POR circuit depends on electrical characteristics of the NMOS transistor switch;  
       a first pull-up p-channel MOS (PMOS) capacitor having a first terminal coupled to the voltage power supply and a second terminal coupled to the drain of the NMOS transistor;  
       a first CMOS inverter having an input terminal coupled to the second terminal of the first PMOS capacitor; a first pull-down p-channel MOS (PMOS) capacitor having a first terminal coupled to an output of the first CMOS inverter and the A second terminal coupled to the electrical ground;  
       a second CMOS inverter having an input terminal electrically coupled to the output terminal of the first CMOS converter;  
       a second pull-up p-channel MOS (PMOS) capacitor having a first terminal electrically coupled to an output terminal of the second CMOS inverter and a second terminal coupled to the power supply voltage;  
       a third CMOS inverter having an input terminal electrically coupled to the output terminal of the second CMOS inverter;  
       a second pull-down p-channel(PMOS) capacitor having a first terminal coupled to the electrical ground and a second terminal electrically coupled to an output terminal of the third CMOS inverter;  
       a fourth CMOS inverter having an input terminal coupled to the output terminal of the third CMOS inverter; and  
       a fifth CMOS inverter having an input terminal electrically coupled to the output terminal of the fourth CMOS inverter and an output terminal which forms an output of the CMOS POR circuit.  
     
     
       12. A digital system, comprising: 
       a digital circuit connected to a power supply voltage;  
       a power-on reset circuit coupled to the power supply voltage and the digital circuit, the power-on reset circuit comprising:  
       a p-channel MOS (PMOS) transistor having a source electrically coupled to a power supply voltage and a gate electrically coupled to an electrical ground;  
       a first NMOS transistor connected as a diode having a gate electrically coupled to a drain and to a second terminal of a first CMOS capacitor;  
       a second NMOS transistor connected as a diode having a gate electrically coupled to a drain and to a source of the first NMOS transistor;  
       a low-threshold n-channel MOS (NMOS) transistor connected as a diode with a gate electrically coupled to a drain and to a source of the second NMOS transistor;  
       a pull-down resistor having a first terminal and a second terminal, the first terminal is electrically coupled in series with the source of the p-channel MOS transistor and the second terminal electrically coupled to the electrical ground so that the current flowing from the power supply voltage through the pull-down resistor is limited;  
       a transistor switch having a source coupled to the electrical ground and a gate electrically coupled to the first terminal of the null-down resistor for detecting the rising edge of the power voltage supply, wherein a trip point of the POR circuit depends on the characteristics of the transistor switch;  
       a pull-up resistor having a first terminal and a second terminal, the first terminal being electrically coupled to the power supply voltage and the second terminal is being coupled to a drain of the transistor switch; and  
       a plurality of MOS inverters coupled in series to one another and an input terminal of a, first MOS inverter is electrically coupled to the second terminal of the pull-up resistor and an output terminal of a last MOS inverter forming an output of the power-on reset circuit.  
     
     
       13. A digital system, comprising: 
       a digital circuit connected to a power supply voltage;  
       a power-on reset circuit coupled to the power supply voltage and the digital circuit, power-on reset circuit comprising:  
       a first p-channel MOS (PMOS) transistor having a source electrically coupled to a power supply voltage and a gate electrically coupled to an electrical ground;  
       a second p-channel transistor with a drain electrically coupled to the source of the p-channel MOS transistor and a gate electrically coupled to the drain;  
       a pull-down resistor having a first terminal coupled to the source of the second PMOS transistor, and a second terminal electrically coupled to the electrical ground so that current flowing from the power supply voltage to ground is limited;  
       an n-channel MOS (NMOS) transistor having a gate electrically coupled to the first terminal of the resistor and a source electrically coupled to the electrical ground;  
       a first pull-up n-channel MOS (NMOS) transistor having a drain electrically coupled to the power supply voltage, a gate coupled to the electrical ground, and a source electrically coupled to the drain of the NMOS transistor, wherein a trip point of the power-on reset circuit depends on the circuit of the NMOS transistor;  
       a first pull-up p-channel MOS (PMOS) capacitor having a first terminal coupled to the voltage power supply and a second terminal coupled to a drain of the NMOS transistor;  
       a first MOS inverter having an input terminal coupled to the second terminal of the first PMOS capacitor;  
       a first pull-down p-channel MOS (PMOS) capacitor having a first terminal coupled to an output of the first MOS inverter and a second terminal coupled to the electrical ground;  
       a second MOS inverter having an input terminal electrically coupled to the output terminal of the first MOS inverter;  
       a second pull-up p-channel MOS (PMOS) capacitor having a first terminal electrically coupled to the an output terminal of the second MOS inverter and a second terminal coupled to the power supply voltage;  
       a third MOS inverter having an input terminal electrically coupled to the output terminal of the second MOS inverter;  
       a second pull-down MOS (PMOS) capacitor having a first terminal coupled to the electrical ground and a second terminal electrically coupled to an output terminal of the third MOS inverter;  
       a fourth MOS inverter having an input terminal coupled to the output terminal of the third MOS inverter; and  
       a fifth MOS inverter having an input terminal electrically coupled to an output terminal of the fourth terminal and an output terminal forming an output of the power-on reset circuit.