Method for fabricating an array substrate for a liquid crystal display with an insulating stack made from TFT layers between crossed conductors

Abstract

An array substrate for use in a liquid crystal display device is fabricated by the steps of forming a first metal layer on a substrate, patterning the first metal layer to form a gate line, a gate electrode, a gate pad, a first shorting bar, and a second shorting bar, forming a gate insulation layer, a pure amorphous silicon layer, a doped amorphous silicon layer and a second metal layer to cover the patterned first metal layer, patterning the second metal layer and the doped amorphous silicon layer to form first, second and third through-holes and first and second grooves to expose a portion of the pure amorphous silicon layer, the first and second grooves creating an isolated portions of the second metal layer, forming a passivation layer to cover the patterned second metal layer, forming a source electrode, a drain electrode, a data line, a data pad, an insulating segment, and first, second and third contact holes, and forming a pixel electrode, a first connector and a second connector of a transparent conductive material.

What is claimed is:  
     
       1. A method of fabricating an array substrate for a liquid crystal display device, comprising the steps of: 
       forming a first metal layer on a substrate;  
       patterning the first metal layer to form a gate line, a gate electrode, a gate pad, a first shorting bar, and a second shorting bar;  
       forming a gate insulation layer, a pure amorphous silicon layer, a doped amorphous silicon layer and a second metal layer to cover the patterned first metal layer;  
       patterning the second metal layer and the doped amorphous silicon layer to form first, second and third through-holes and first and second grooves to expose a portion of the pure amorphous silicon layer, the first and second grooves creating an isolated portions of the second metal layer;  
       forming a passivation layer to cover the patterned second metal layer;  
       forming a source electrode, a drain electrode, a data line, a data pad, an insulating segment, and first, second and third contact holes; and  
       forming a pixel electrode, a first connector and a second connector of a transparent conductive material.  
     
     
       2. The method of fabricating an array substrate according to  claim 1 , wherein the gate electrode extends from the gate line, the gate pad is arranged at a first end of the gate line, and the first shorting bar and the second shorting bar are spaced apart from each other and arranged parallel with the gate line. 
     
     
       3. The method of fabricating an array substrate according to  claim 1 , wherein the source electrode extends from the data line, and the drain electrode is spaced apart from the source electrode. 
     
     
       4. The method of fabricating an array substrate according to  claim 1 , wherein the data pad is arranged at a first end of the data line, and the insulating segment is formed over the first shorting bar. 
     
     
       5. The method of fabricating an array substrate according to  claim 1 , wherein the first contact hole penetrates the data pad, the second contact hole exposes a portion of the first shorting bar, and the third contact hole exposes a portion of the second shorting bar. 
     
     
       6. The method of fabricating an array substrate according to  claim 1 , wherein the pixel electrode is connected with the drain electrode and is located in a pixel region defined by the gate line and the data line. 
     
     
       7. The method of fabricating an array substrate according to  claim 1 , wherein the first connector electrically connects an odd numbered data line to the first shorting bar, and the second connector electrically connects an even numbered data lines to the second shorting bar. 
     
     
       8. The method of fabricating an array substrate according to  claim 1 , wherein the first connector and the second connector contact the data pad through the first contact hole. 
     
     
       9. The method of fabricating an array substrate according to  claim 8 , wherein the first connector contacts the first shorting bar through the second contact hole. 
     
     
       10. The method of fabricating an array substrate according to  claim 8 , wherein the second connector contacts the second shorting bar through the third contact hole. 
     
     
       11. The method of fabricating an array substrate according to  claim 1 , wherein the insulating segment is formed at a crossover point of the first shorting bar and the second connector. 
     
     
       12. The method of fabricating an array substrate according to  claim 11 , wherein the insulating segment is disposed between the first shorting bar and the second connector. 
     
     
       13. The method of fabricating an array substrate according to  claim 12 , wherein the insulating segment includes patterned layers comprising the passivation layer, the second metal layer, the doped amorphous silicon layer and the pure amorphous silicon layer. 
     
     
       14. The method of fabricating an array substrate according to  claim 1 , wherein the transparent conductive material includes at least one of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). 
     
     
       15. The method of fabricating an array substrate according to  claim 1 , wherein the first hole is formed over the gate electrode. 
     
     
       16. The method of fabricating an array substrate according to  claim 1 , wherein the second hole is formed over the first shorting bar. 
     
     
       17. The method of fabricating an array substrate according to  claim 1 , wherein the third hole is formed over the second shorting bar. 
     
     
       18. The method of fabricating an array substrate according to  claim 1 , wherein the isolated metal layer is formed over the first shorting bar. 
     
     
       19. The method of fabricating an array substrate according to  claim 18 , wherein the first groove and the second groove are formed on opposite sides of the isolated metal layer. 
     
     
       20. The method of fabricating an array substrate according to  claim 18 , wherein the first groove is formed in a portion of the second metal layer between the first shorting bar and the second shorting bar. 
     
     
       21. The method of fabricating an array substrate according to  claim 1 , wherein the second metal layer includes at least molybdenum (Mo) material.