Nonvolatile semiconductor memory device
Abstract
This nonvolatile semiconductor memory device includes a word line regulator circuit 22, which supplies a voltage to a word line, a program/erase control circuit 21, which outputs a write control signal to the word line regulator circuit 22, and a pulse voltage step width storage circuit 23, which stores information of a voltage increment DeltaVg. The word line regulator circuit 22 supplies a voltage to a word line according to the write control signal from the program/erase control circuit 21 based on the information of a voltage increment DeltaVg stored in the pulse voltage step width storage circuit 23. A voltage increment DeltaVg by which a threshold voltage change of a memory cell becomes a predetermined voltage can be set for each chip by the pulse voltage step width storage circuit 23. Consequently, a highly reliable multi-valued write operation can be performed.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. An electrically writable and erasable nonvolatile semiconductor memory device composed of one or more chips and having memory cells respectively constituted by a floating gate field effect transistor including a control gate, a drain, a source and a floating gate, wherein charged states corresponding to three or more values are generated in the floating gate, comprising:
write means that, at the time of write operation for generating one of two or more charged states of the floating gate corresponding to two or more values, performs a first step of applying a write pulse being a positive write start voltage to the control gate, and thereafter repeatedly performs a second step of applying a write pulse to the control gate of the transistor of a memory cell which is not judged to be in a predetermined charged state, wherein the write pulse in the second step is repeatedly raised by a voltage increment until the transistor of the memory cell becomes the predetermined charged state, wherein
a voltage increment setting means for setting the voltage increment in the second step for each chip.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein
the write means includes:
voltage supply means for supplying a voltage to the control gate;
write control means for outputting a write control signal to the voltage supply means; and
storage means for storing information of the voltage increment; and
the voltage supply means successively supplies voltages raised by the voltage increment based on the information of the voltage increment stored in the storage means to the control gate according to a write control signal from the write control means.
3. The nonvolatile semiconductor memory device according to claim 2 , wherein
information of the voltage increment by which a change of the threshold voltage of a memory cell obtained by a test of a write characteristic becomes a predetermined voltage is stored in the storage means.
4. The nonvolatile semiconductor memory device according to claim 2 , wherein
a memory cell having the same constitution as the memory cell is used as the storage means.
5. The nonvolatile semiconductor memory device according to claim 2 , wherein
the voltage supply means supplies a voltage generated by a resistive potential divider to the control gate.
6. The nonvolatile semiconductor memory device according to claim 1 , wherein
the write means includes:
voltage supply means for supplying a voltage to the control gate;
write control means for outputting a write control signal to the voltage supply means; and
storage means for storing a numerical value corresponding to the voltage increment as information of the voltage increment;
the write control means successively adds a numerical value corresponding to the voltage increment stored in the storage means to the positive write start voltage, and outputs a write control signal representing the positive write start voltage and added results; and
the voltage supply means supplies a voltage corresponding to the write control signal from the write control means to the control gate.Cited by (0)
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