Common mode feedback technique for a low voltage charge pump

Abstract

A charge pump includes a first current source, a second current source, and a current mirror. The first current source is included to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core. The second current source is included to receive the common mode output voltage from the charge pump core. A first input of the current mirror receives a signal from the first current source, and a second input of the current mirror receives a signal from the second current source.

What is claimed is:  
     
       1. A charge pump, comprising: 
       a first current source to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core;  
       a second current source to receive the common mode output voltage from the charge pump core; and  
       a current mirror, a first input of the current mirror to receive a signal from the first current source, and a second input of the current mirror to receive a signal from the second current source.  
     
     
       2. A charge pump, comprising: 
       a first current source to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core;  
       a second current source to receive the common mode output voltage from the charge pump core;  
       a current mirror, a first input of the current mirror to receive a signal from the first current source, and a second input of the current mirror to receive a signal from the second current source; and  
       a third current source to manipulate a current of the charge pump core to approximately equal a current that is received from the current mirror.  
     
     
       3. The charge pump according to  claim 2 , further including a differential output coupled to the charge pump core. 
     
     
       4. A charge pump, comprising: 
       a current mirror;  
       a first current source, including a first transistor to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core, and a second transistor to receive a signal from the first transistor and to provide a signal to a first input of the current mirror; and  
       a second current source, including a third transistor to receive a first signal with which the common mode output voltage of the charge pump core may be obtained, a fourth transistor to receive a second signal with which the common mode output voltage of the charge pump core may be obtained, wherein the third transistor is connected in parallel with the fourth transistor, and a fifth transistor to receive a signal from the third transistor or the fourth transistor and to provide a signal to a second input of the current mirror.  
     
     
       5. A charge pump, comprising: 
       a current mirror;  
       a first current source, including a first transistor to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core, and a second transistor to receive a signal from the first transistor and to provide a signal to a first input of the current mirror;  
       a second current source, including a third transistor to receive a first signal with which the common mode output voltage of the charge pump core may be obtained, a fourth transistor to receive a second signal with which the common mode output voltage of the charge pump core may be obtained, wherein the third transistor is connected in parallel with the fourth transistor, and a fifth transistor to receive a signal from the third transistor or the fourth transistor and to provide a signal to a second input of the current mirror; and  
       a third current source to manipulate a current of the charge pump core to approximately equal a current that is received from the current mirror.  
     
     
       6. A charge pump, comprising: 
       a current mirror;  
       a first current source, including a first transistor to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core, and a second transistor to receive a signal from the first transistor and to provide a signal to a first input of the current mirror;  
       a second current source, including a third transistor to receive a first signal with which the common mode output voltage of the charge pump core may be obtained, a fourth transistor to receive a second signal with which the common mode output voltage of the charge pump core may be obtained, wherein the third transistor is connected in parallel with the fourth transistor, and a fifth transistor to receive a signal from the third transistor or the fourth transistor and to provide a signal to a second input of the current mirror, wherein the charge pump core includes a third current source, a fourth current source, a fifth current source, and a sixth current source, the third current source switchably coupled in series with the fifth current source, the third current source switchably coupled in series with the sixth current source, the fourth current source switchably coupled in series with the fifth current source, and the fourth current source switchably coupled in series with the sixth current source.  
     
     
       7. The charge pump according to  claim 6 , wherein a seventh current source is connected in parallel with the third current source, and an eighth current source is connected in parallel with the fourth current source. 
     
     
       8. The charge pump according to  claim 6 , wherein a seventh current source is connected in parallel with the fifth current source, and an eighth current source is connected in parallel with the sixth current source. 
     
     
       9. A charge pump, comprising: 
       a current mirror;  
       a first current source, including a first transistor to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core, and a second transistor to receive a signal from the first transistor and to provide a signal to a first input of the current mirror;  
       a second current source, including a third transistor to receive a first signal with which the common mode output voltage of the charge pump core may be obtained, a fourth transistor to receive a second signal with which the common mode output voltage of the charge pump core may be obtained, wherein the third transistor is connected in parallel with the fourth transistor, and a fifth transistor to receive a signal from the third transistor or the fourth transistor and to provide a signal to a second input of the current mirror, wherein the current mirror includes a fifth transistor and a sixth transistor, and a gate of the sixth transistor is coupled to a drain of the sixth transistor, and the gate of the sixth transistor is coupled to a gate of the fifth transistor.  
     
     
       10. The charge pump according to  claim 5 , further including a differential output coupled to the charge pump core. 
     
     
       11. A phase locked loop circuit, comprising: 
       a detector to compare a relative timing between a first signal and a second signal;  
       a charge pump coupled to the detector, including  
       a current mirror,  
       a first current source, including a first transistor to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core, and a second transistor to receive a signal from the first transistor and to provide a signal to a first input of the current mirror, and  
       a second current source, including a third transistor to receive a first signal with which the common mode output voltage of the charge pump core may be obtained, a fourth transistor to receive a second signal with which the common mode output voltage of the charge pump core may be obtained, wherein the third transistor is connected in parallel with the fourth transistor, and a fifth transistor to receive a signal from the third transistor or the fourth transistor and to provide a signal to a second input of the current mirror; and  
       an oscillator coupled to the charge pump.  
     
     
       12. A phase locked loop circuit, comprising: 
       a detector to compare a relative timing between a first signal and a second signal;  
       a charge pump coupled to the detector, including  
       a current mirror,  
       a first current source, including a first transistor to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core, and a second transistor to receive a signal from the first transistor and to provide a signal to a first input of the current mirror, and  
       a second current source, including a third transistor to receive a first signal with which the common mode output voltage of the charge pump core may be obtained, a fourth transistor to receive a second signal with which the common mode output voltage of the charge pump core may be obtained, wherein the third transistor is connected in parallel with the fourth transistor, and a fifth transistor to receive a signal from the third transistor or the fourth transistor and to provide a signal to a second input of the current mirror, wherein the charge pump further includes a third current source to manipulate a current of the charge pump core to approximately equal a current that is received from the current mirror; and an oscillator coupled to the charge pump.  
     
     
       13. A phase locked loop circuit, comprising: 
       a detector to compare a relative timing between a first signal and a second signal;  
       a charge pump coupled to the detector, including  
       a current mirror,  
       a first current source, including a first transistor to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core, and a second transistor to receive a signal from the first transistor and to provide a signal to a first input of the current mirror, and  
       a second current source, including a third transistor to receive a first signal with which the common mode output voltage of the charge pump core may be obtained, a fourth transistor to receive a second signal with which the common mode output voltage of the charge pump core may be obtained, wherein the third transistor is connected in parallel with the fourth transistor, and a fifth transistor to receive a signal from the third transistor or the fourth transistor and to provide a signal to a second input of the current mirror, wherein the charge pump core includes a third current source, a fourth current source, a fifth current source, and a sixth current source, the third current source switchably coupled in series with the fifth current source, the third current source switchably coupled in series with the sixth current source, the fourth current source switchably coupled in series with the fifth current source, and the fourth current source switchably coupled in series with the sixth current source; and an oscillator coupled to the charge pump.  
     
     
       14. The phase locked loop circuit according to  claim 13 , wherein a seventh current source is connected in parallel with the third current source, and an eighth current source is connected in parallel with the fourth current source. 
     
     
       15. The phase locked loop circuit according to  claim 13 , wherein a seventh current source is connected in parallel with the fifth current source, and an eighth current source is connected in parallel with the sixth current source. 
     
     
       16. A phase locked loop circuit, comprising: 
       a detector to compare a relative timing between a first signal and a second signal;  
       a charge pump coupled to the detector, including  
       a current mirror,  
       a first current source, including a first transistor to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core, and a second transistor to receive a signal from the first transistor and to provide a signal to a first input of the current mirror, and  
       a second current source, including a third transistor to receive a first signal with which the common mode output voltage of the charge pump core may be obtained, a fourth transistor to receive a second signal with which the common mode output voltage of the charge pump core may be obtained, wherein the third transistor is connected in parallel with the fourth transistor, and a fifth transistor to receive a signal from the third transistor or the fourth transistor and to provide a signal to a second input of the current mirror, wherein the current mirror includes a fifth transistor and a sixth transistor, and a gate of the sixth transistor is coupled to a drain of the sixth transistor, and the gate of the sixth transistor is coupled to a gate of the fifth transistor; and  
       an oscillator coupled to the charge pump.  
     
     
       17. The phase locked loop circuit according to  claim 12 , wherein the charge pump includes a differential output coupled to the charge pump core. 
     
     
       18. A signal transporting circuit, comprising: 
       a phase locked loop circuit, including  
       a detector,  
       a charge pump coupled to the detector, having  
       a current mirror,  
       a first current source, including a first transistor to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core, and a second transistor to receive a signal from the first transistor and to provide a signal to a first input of the current mirror, and  
       a second current source, including a third transistor to receive a first signal with which the common mode output voltage of the charge pump core may be obtained, a fourth transistor to receive a second signal with which the common mode output voltage of the charge pump core may be obtained, wherein the third transistor is connected in parallel with the fourth transistor, and a fifth transistor to receive a signal from the third transistor or the fourth transistor and to provide a signal to a second input of the current mirror, and  
       an oscillator coupled to the charge pump; and  
       a transmission speed adjusting circuit to receive a signal from the phase locked loop circuit and to modify a number of channels of the signal.  
     
     
       19. The signal transporting circuit according to  claim 18 , wherein the signal transporting circuit is a transmitter. 
     
     
       20. The signal transporting circuit according to  claim 18 , wherein the signal transporting circuit is a receiver. 
     
     
       21. The signal transporting circuit according to  claim 18 , wherein the transmission speed adjusting circuit is a multiplexer. 
     
     
       22. The signal transporting circuit according to  claim 18 , wherein the transmission speed adjusting circuit is a de-multiplexer. 
     
     
       23. The signal transporting circuit according to  claim 18 , wherein the oscillator is a voltage controlled oscillator (“VCO”). 
     
     
       24. The signal transporting circuit according to  claim 18 , wherein the charge pump further includes a third current source to manipulate a current of the charge pump core to approximately equal a current that is received from the current mirror. 
     
     
       25. The signal transporting circuit according to  claim 18 , wherein the charge pump core includes a third current source, a fourth current source, a fifth current source, and a sixth current source, the third current source switchably coupled in series with the fifth current source, the third current source switchably coupled in series with the sixth current source, the fourth current source switchably coupled in series with the fifth current source, and the fourth current source switchably coupled in series with the sixth current source. 
     
     
       26. The signal transporting circuit according to  claim 25 , wherein a seventh current source is connected in parallel with the third current source, and an eighth current source is connected in parallel with the fourth current source. 
     
     
       27. The signal transporting circuit according to  claim 25 , wherein a seventh current source is connected in parallel with the fifth current source, and an eighth current source is connected in parallel with the sixth current source. 
     
     
       28. The signal transporting circuit according to  claim 18 , wherein the current mirror includes a fifth transistor and a sixth transistor, and a gate of the sixth transistor is coupled to a drain of the sixth transistor, and the gate of the sixth transistor is coupled to a gate of the fifth transistor. 
     
     
       29. The signal transporting circuit according to  claim 18 , wherein the charge pump includes a differential output coupled to the charge pump core. 
     
     
       30. A method of equating a current of a common mode feedback circuit and a current of a charge pump core, comprising: 
       setting a common mode output voltage of the charge pump core;  
       degenerating a first current of a first current source;  
       degenerating a second current of a second current source;  
       equating the first current and the second current; and  
       equating the second current and the current of the charge pump core, wherein the charge pump core includes a third current source, a fourth current source, a fifth current source, and a sixth current source, and a seventh current source is coupled in parallel with at least one of the third current source and the fifth current source, and an eighth current source is coupled in parallel with at least one of the fourth current source and the sixth current source.  
     
     
       31. The method according to  claim 30 , wherein equating the first current and the second current is performed by a current mirror. 
     
     
       32. The method according to  claim 30 , wherein degenerating the first current of the first current source is performed by a first transistor and degenerating the second current of the second current source is performed by a second transistor.