Floating point overflow and sign detection

Abstract

A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

What is claimed is:  
     
       1. A floating point multiply-accumulate circuit comprising: 
       an exponent path including:  
       an exponent summer to sum two input exponents having a first weight to produce a product exponent;  
       an exponent conversion unit coupled to the output of the exponent summer, to convert the product exponent to a second weight; and  
       an exponent accumulation stage to accumulate the converted product exponent and to choose a larger exponent from the converted product exponent and an accumulated exponent; and  
       a mantissa path including:  
       a mantissa multiplier to multiply two input mantissas and produce a product mantissa in carry-save format that includes a sum field and a carry field;  
       a mantissa shifter to shift the sum field and the carry field responsive to the exponent conversion unit in the exponent path; and  
       a mantissa accumulator to accumulate shifted product mantissas in carry-save format, the mantissa accumulator including an overflow detection circuit responsive to two most significant bits of a sum field output from the mantissa accumulator.  
     
     
       2. The floating point multiply-accumulate circuit of  claim 1  wherein the overflow detection circuit comprises an exclusive-or gate. 
     
     
       3. The floating point multiply-accumulate circuit of  claim 1  wherein the exponent conversion unit is configured to zero the least significant five bits of the product exponent. 
     
     
       4. The floating point multiply-accumulate circuit of  claim 1  wherein the mantissa shifter is configured to shift the sum field and carry field of the product mantissa by a number of bit positions equal to a value of the least significant five bits of the product exponent. 
     
     
       5. The floating point multiply-accumulate circuit of  claim 1 , wherein the mantissa accumulator comprises four-to-two compressors. 
     
     
       6. The floating point multiply-accumulate circuit of  claim 1  further comprising a post-normalization stage to produce a normalized floating point resultant. 
     
     
       7. The floating point multiply-accumulate circuit of  claim 6  wherein the post-normalization stage includes a sign detection circuit. 
     
     
       8. The floating point multiply-accumulate circuit of  claim 7  further comprising a magnitude comparator in parallel with the mantissa accumulator, wherein the sign detection circuit is responsive to the magnitude comparator. 
     
     
       9. The floating point multiply-accumulate circuit of  claim 6  wherein the post-normalization stage is configured to be turned off until accumulation is complete. 
     
     
       10. The floating point multiply-accumulate circuit of  claim 1  wherein the exponent conversion unit is configured to convert the product exponent to have a least significant bit weight equal to thirty-two. 
     
     
       11. A method performed within a programmable digital computer, comprising: 
       multiplying two floating point mantissas and summing two floating point exponents to form a product;  
       converting the product to have a different least significant bit weight exponent field;  
       accumulating the converted product in carry-save format;  
       detecting overflow as a function of two most significant bits of a sum field of an accumulated product; and  
       post-normalizing the accumulated product.  
     
     
       12. The method of  claim 11  wherein accumulating the product comprises adding a first plurality of products with a last product, the method further comprising turning off post-normalization until the last product is accumulated. 
     
     
       13. The method of  claim 11  wherein converting comprises: 
       shifting a mantissa of the product by an amount equal to the value of the least significant five bits of the exponent of the product; and  
       zeroing the least significant five bits of an exponent of the product.  
     
     
       14. The method of  claim 11  wherein accumulating comprises: 
       comparing an exponent of a first converted product to an exponent of a second converted product;  
       conditionally shifting right by a fixed amount the mantissa of the converted product having a smaller exponent;  
       selecting the larger exponent as a resultant exponent; and  
       producing a resultant mantissa from a mantissa of the first converted product and a mantissa of the second converted product.  
     
     
       15. The method of  claim 14  wherein conditionally shifting right comprises selecting one of two inputs of a multiplexor. 
     
     
       16. The method of  claim 14  wherein producing a resultant mantissa comprises selecting the mantissa of the first converted product if the exponent of the first converted product is more than one greater than the exponent of the second converted product. 
     
     
       17. The method of  claim 14  wherein producing a resultant mantissa comprises adding mantissas of the first and second converted products to produce a resultant mantissa. 
     
     
       18. The method of  claim 14  wherein conditionally shifting right comprises: 
       when the exponent of the first converted product is one greater than the exponent of the second converted product, shifting a mantissa of the second converted product thirty-two bit positions to the right.  
     
     
       19. The method of  claim 11  wherein post-normalizing the accumulated product comprises: 
       detecting a sign of the accumulated product; and  
       conditionally negating the accumulated product responsive to the sign.  
     
     
       20. The method of  claim 19  wherein detecting a sign comprises comparing a magnitude of the mantissas of the first and second converted products.