Method for fabricating merged dram with logic semiconductor device

Abstract

A method is disclosed for fabricating an MDL (Merged DRAM Logic) semiconductor device, in which silicide is formed on a logic region and a memory region selectively for enhancing device reliability. The method includes the steps of (a) providing a substrate having a first region and a second region adjoining the first region, (b) forming a first gate forming material layer in the first region, (c) forming a second gate forming material layer in the first region having the first gate forming material layer formed therein and the second region, (d) selectively patterning the second gate forming material layer to form second gates in the second region and a boundary dummy pattern layer at a boundary area of the first and second regions, and (e) selectively patterning the first gate forming material layer to form first gates in the first region.

What is claimed is:  
     
       1. A method for fabricating a memory-logic combined semiconductor device, the method comprising the steps of: 
       (a) providing a substrate having a first region and a second region adjoining the first region;  
       (b) forming a first gate forming material layer in the first region;  
       (c) forming a second gate forming material layer in the second region and in the first region having the first gate forming material layer formed therein;  
       d) selectively patterning the second gate forming material layer simultaneously with completely removing the second gate forming material layer in the first region except in a boundary area between the first and second regions to form second gates in the second region and to form a boundary dummy pattern layer at the boundary area of the first and second regions; and  
       (e) selectively patterning the first gate forming material layer to form first gates in the first region.  
     
     
       2. A method as claimed in  claim 1 , wherein the first gate forming material layer is formed of polysilicon, and the method further comprises the step of (f) forming a cap insulating layer on the first gate forming material layer. 
     
     
       3. A method as claimed in  claim 1 , wherein the second gate forming material layer is a stack of a polysilicon layer and a silicide layer, and the method further comprises the step of (g) forming a cap insulating layer on the silicide layer. 
     
     
       4. A method as claimed in  claim 1 , further comprising the step of: 
       (h) forming first and second gate oxide films of different thicknesses under the first and second gate forming material layers, respectively, before formation of the first and second gate forming material layers.  
     
     
       5. A method as claimed in  claim 1 , further comprising the step of: 
       (l) forming source/drain on sides of the first and second gates in the first and second regions by conducting separately impurity ion injection processes for the first and second regions.  
     
     
       6. A method as claimed in  claim 1 , further comprising the step of: 
       (j) forming a gap fill forming material layer only in the second region by forming a sidewall forming material layer and the gap fill forming material layer in succession on an entire surface of the substrate after formation of the first and second gates and by subjecting the sidewall forming material layer and the gap fill forming material layer to anisotropic etching.  
     
     
       7. A method as claimed in  claim 1 , wherein the first and second regions are logic and memory regions, respectively. 
     
     
       8. A method as claimed in  claim 1 , wherein the memory-logic combined semiconductor device is a Merged DRAM Logic (MDL) device or an Embedded DRAM Logic (EDL) device. 
     
     
       9. A method for fabricating an MDL semiconductor device having first and second regions with different characteristics, the method comprising the steps of: 
       (a) providing a substrate including first and second regions;  
       (b) forming a first gate oxide film, a first gate forming material layer, and a first capping layer on the first region;  
       (c) forming a second gate oxide film, a second gate forming material layer, a second capping layer on an entire surface of the substrate after the step (b);  
       (d) selectively patterning the second gate oxide film, the second gate forming material layer, and the second capping layer to form gates in the second region simultaneously with removing the second capping layer, and the first capping layer in the first region at the same time and to form a boundary dummy pattern layer at a boundary area of the first and second regions;  
       (e) forming a source/drain in the second region; and  
       (f) after the source/drain is formed in the second region, selectively removing the first gate oxide film and the first gate forming material on the first region to form gates in the first region.  
     
     
       10. A method as claimed in  claim 9 , further comprising the steps of: 
       (g) forming LDD regions in the first region;  
       (h) after the LDD regions are formed in the first region, forming a sidewall forming material layer and a gap fill forming material layer in succession on an entire surface of the substrate, and etching the gap fill forming material layer in the first region.  
     
     
       11. A method as claimed in  claim 10 , further comprising the steps of: 
       (i) forming gate sidewalls at sides of the gates in the first region;  
       (j) forming a source/drain between the gates in the first region; and  
       (k) forming silicide layers on surfaces of the gates and the source/drain in the first region.  
     
     
       12. A method as claimed in  claim 9 , wherein the first region is a logic device region, and the second region is a memory device region. 
     
     
       13. A method as claimed in  claim 10 , wherein the second region is masked by the gap fill forming material layer in formation of the LDD regions in the first region. 
     
     
       14. A method as claimed in  claim 10 , wherein the gap fill forming material layer is remained between the gates in the second region by blanket etching using differences in distances between the gates in the first and second regions, when removing the gap fill forming material layer from the first region in the step (h). 
     
     
       15. A method as claimed in  claim 9 , further comprising the step of (l) forming a silicide layer of a refractory metal between the second gate forming material layer and the second capping layer. 
     
     
       16. A method as claimed in  claim 15 , wherein the silicide layer in the first region is removed when the gates in the second region are patterned such that the silicide layer exists only on top of the gates in the second region, but not on top of the gates in the first region once the gates in the first and second regions are formed. 
     
     
       17. A method as claimed in  claim 9 , wherein the first gate oxide film has a thickness greater than a thickness of the second gate oxide film. 
     
     
       18. A method as claimed in  claim 11  wherein impurity concentrations of the source/drain in the first region and the source/drain in the second region differ from each other. 
     
     
       19. A method as claimed in  claim 10 , wherein the sidewall forming material layer includes a stack of an oxide film and a nitride film, and the gap fill forming material layer is formed of one selected from a group of materials including BPSG, PSG, HDP oxide film, SOG, and USG. 
     
     
       20. A method for fabricating a memory-logic combined semiconductor device, the method comprising the steps of: 
       (a) providing a substrate having a first region and a second region adjoining the first region;  
       (b) forming a first gate forming material layer in the first region;  
       (c) forming a second gate forming material layer in the second region and in the first region having the first gate forming material layer formed therein;  
       (d) selectively patterning the second gate forming material layer to form second gates in the second region and to form a boundary dummy pattern layer at a boundary area of the first and second regions;  
       (e) selectively patterning the first gate forming material layer to form first gates in the first region; and  
       (f) forming a gap fill forming material layer only in the second region by forming a sidewall forming material layer and the gap fill forming material layer in succession on an entire surface of the substrate after formation of the first and second gates and by subjecting the sidewall forming material layer and the gap fill forming material layer to anisotropic etching.