Apparatus and method for leadless packaging of semiconductor devices

Abstract

The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

What is claimed is:  
     
       1. A method for fabricating a plurality of vertically stacked, interconnected and leadless semiconductor packages, comprising: 
       supporting a substrate having a plurality of first semiconductor chips formed therein, the first chips having a first plurality of bond pads exposed at an upper surface of the substrate;  
       positioning a plurality of second semiconductor chips onto the substrate, each second chip being positioned on a single first chip and having a second plurality of bond pads;  
       depositing a plurality of interconnections onto the first chips and the second chips that extend between corresponding bond pads on the first and second chips;  
       singulating the substrate to obtain a plurality of separated semiconductor packages, wherein singulating the substrate further comprises thinning the substrate at a lower surface that opposes the upper surface to obtain a thinned substrate, and dicing the thinned substrate to form a plurality of separated semiconductor packages; and  
       depositing a plurality of castellations to the first chips that extend outwardly from the first plurality of bond pads.  
     
     
       2. The method according to  claim 1  wherein the step of positioning is further comprised of bonding the second chips to the substrate using an adhesive. 
     
     
       3. The method according to  claim 1  wherein the step of bonding is further comprised of applying one side of a double-backed adhesive tape to the substrate; and disposing the second chip onto an opposing side of the double-backed adhesive tape. 
     
     
       4. The method according to  claim 1  wherein the step of depositing a plurality of interconnections further comprises: depositing a dielectric layer onto selected surface portions of the first and second chips; and forming a metallic film on the dielectric layer. 
     
     
       5. The method according to  claim 1  wherein the step of depositing a plurality of castellations further comprises: depositing a dielectric layer onto selected surface portions of the first chips; and forming a metallic film on the dielectric layer. 
     
     
       6. The method according to  claim 1  wherein the step of singulating the substrate further comprises: forming a plurality of holes that project through the substrate that are positioned between adjacent first chips; thinning the substrate at a lower surface that opposes the upper surface to obtain a thinned substrate; and dicing the thinned substrate along a direction that substantially bisects the holes. 
     
     
       7. The method according to  claim 6  wherein the step of thinning the substrate is further comprised of backgrinding the substrate. 
     
     
       8. The method according to  claim 1 , further comprising applying a dielectric layer to the second semiconductor chips that substantially encapsulates the second chips and at least partially extends onto the first chips. 
     
     
       9. A method for fabricating a plurality of vertically stacked, interconnected and leadless semiconductor packages, comprising: 
       supporting a substrate having a plurality of first semiconductor chips formed therein, the first chips having a first plurality of bond pads exposed at an upper surface of the substrate;  
       positioning a plurality of second semiconductor chips onto the substrate, each second chip being positioned on a single first chip and having a second plurality of bond pads;  
       depositing a plurality of interconnections onto the first chips and the second chips that extend between corresponding bond pads on the first and second chips;  
       singulating the substrate to obtain a plurality of separated semiconductor packages, wherein singulating the substrate further comprises forming a plurality of holes that project through the substrate that are positioned between adjacent first chips, thinning the substrate at a lower surface that opposes the upper surface to obtain a thinned substrate, and dicing the thinned substrate along a direction that substantially bisects the holes; and  
       depositing a plurality of castellations to the first chips that extend outwardly from the first plurality of bond pads.  
     
     
       10. The method according to  claim 9  wherein the step of positioning is further comprised of bonding the second chips to the substrate using an adhesive. 
     
     
       11. The method according to  claim 9  wherein the step of bonding is further comprised of applying one side of a double-backed adhesive tape to the substrate; and disposing the second chip onto an opposing side of the double-backed adhesive tape. 
     
     
       12. The method according to  claim 9  wherein the step of depositing a plurality of interconnections further comprises: depositing a dielectric layer onto selected surface portions of the first and second chips; and forming a metallic film on the dielectric layer. 
     
     
       13. The method according to  claim 9  wherein the step of depositing a plurality of castellations further comprises: depositing a dielectric layer onto selected surface portions of the first chips; and forming a metallic film on the dielectric layer. 
     
     
       14. The method according to  claim 9  wherein the step of thinning the substrate is further comprised of backgrinding the substrate. 
     
     
       15. The method according to  claim 9 , further comprising applying a dielectric layer to the second semiconductor chips that substantially encapsulates the second chips and at least partially extends onto the first chips. 
     
     
       16. A method for fabricating a plurality of vertically stacked, interconnected and leadless semiconductor packages, comprising: 
       supporting a substrate having a plurality of first semiconductor chips formed therein, the first chips having a first plurality of bond pads exposed at an upper surface of the substrate;  
       positioning a plurality of second semiconductor chips onto the substrate, each second chip being positioned on a single first chip and having a second plurality of bond pads;  
       depositing a plurality of interconnections onto the first chips and the second chips that extend between corresponding bond pads on the first and second chips;  
       singulating the substrate to obtain a plurality of separated semiconductor packages, wherein singulating the substrate further comprises forming a plurality of holes that project through the substrate that are positioned between adjacent first chips, thinning the substrate by backgrinding the substrate at a lower surface that opposes the upper surface to obtain a thinned substrate, and dicing the thinned substrate along a direction that substantially bisects the holes; and  
       depositing a plurality of castellations to the first chips that extend outwardly from the first plurality of bond pads.  
     
     
       17. The method according to  claim 16  wherein the step of positioning is further comprised of bonding the second chips to the substrate using an adhesive. 
     
     
       18. The method according to  claim 16  wherein the step of bonding is further comprised of applying one side of a double-backed adhesive tape to the substrate; and disposing the second chip onto an opposing side of the double-backed adhesive tape. 
     
     
       19. The method according to  claim 16  wherein the step of depositing a plurality of interconnections further comprises: depositing a dielectric layer onto selected surface portions of the first and second chips; and forming a metallic film on the dielectric layer. 
     
     
       20. The method according to  claim 16  wherein the step of depositing a plurality of castellations further comprises: depositing a dielectric layer onto selected surface portions of the first chips; and forming a metallic film on the dielectric layer.