Serialized HDSL multiplexer - demultiplexer protocol

Abstract

A high bit rate digital subscriber line (HDSL) communications scheme employs a serialized multiplexer—demultiplexer protocol, that enables both HDSL channels to be successfully transmitted over an asynchronous, serialized communication link. A service channel supplies control information used by a far end device to extract each HDSL channel from the serialized bit stream. A data channel interface circuit combines a pair of data channel segments of two 784 kbps HDSL channels into a standard 1.544 Mbps T1 serial data stream. The data channel interface circuit contains a register bank which stores embedded operations channel (EOC) information extracted from the two HDSL channels. Auxiliary HDSL signaling information stored in the data channel interface circuit is controllably accessed by a communications control processor for application to an output multiplexer. A framer unit supervises the operation of output multiplexer controllably and injects auxiliary (framing and time alignment) service channel signals to the output multiplexer. The framing structure of the serialized HDSL protocol provides a contiguous sequence of framing bits, HDSL asynchronous channel bits, bit-stuffing majority bits, a stuffing bit, a signaling bit, and 1.544 Mbps T1 payload bits.

What is claimed is:  
     
       1. A method of conducting high bit rate digital subscriber line (HDSL) communications between a first site and a second site comprising: 
       (a) providing a prescribed HDSL-serialized communication protocol, through which a plurality of HDSL channels are combinable into a serialized bit stream for transmission over a serialized communication link to said second site, and which is operative to incorporate, as part of said serialized bit stream, control information that enables said second site to extract and reassemble each HDSL channel from said serialized bit stream, each of said plurality of HDSL channels comprising a fraction of a T1 or E1 channel; and  
       (b) at said first site, multiplexing said plurality of HDSL channels in accordance with said prescribed HDSL-serialized communication protocol, so as to produce said serialized bit stream containing said plurality of HDSL channels and said control information for transmission over said prescribed HDSL-serialized communication link to said second site said multiplexing comprising using a FIFO for clock rate adaptation.  
     
     
       2. A method according to  claim 1 , further including the step (c) of transmitting said serialized bit stream containing said plurality of HDSL channels and said control information over a wireless communication link to a wireless communication device associated with said second site. 
     
     
       3. A method according to  claim 1 , wherein said prescribed HDSL-serialized communication protocol is effective to generate a sequence of bits that include framing bits for frame alignment, HDSL asynchronous channel bits for transporting HDSL embedded operations channel bits, bit-stuffing majority bits, a stuffing bit, an auxiliary signaling channel bit, and 1.544 Mbps T1 payload bits. 
     
     
       4. A method according to  claim 1 , further including the steps of: 
       (c) transmitting said serialized bit stream containing said plurality of HDSL channels and said control information over said prescribed HDSL-serialized communication link from said first site to said second site;  
       (d) at said second site, receiving said serialized bit stream containing said plurality of HDSL channels and said control information; and  
       (e) demultiplexing said plurality of HDSL channels from said serialized bit stream.  
     
     
       5. A method according to  claim 4 , wherein step (e) includes detecting a framing bit pattern in said serialized bit stream, and thereafter controllably deriving said plurality of HDSL channels, and embedded operations channel bits from said serialized bit stream. 
     
     
       6. A method according to  claim 5 , wherein step (e) includes adjusting a timing attribute of said serialized bit stream in accordance with bit-stuffing majority bits and stuffing bits, so as to locate said framing bit pattern. 
     
     
       7. An arrangement for conducting high bit rate digital subscriber line (HDSL) communications between a first site and a second site comprising: 
       at said first site, a multiplexer for multiplexing a plurality of HDSL channels in accordance with a prescribed HDSL-serialized communication protocol, which is effective to combine a plurality of HDSL channels into a serialized bit stream for transmission over a serial communication link to said second site, and which is effective to incorporate, as part of said serialized bit stream, control information that enables said second site to extract and reassemble each HDSL channel from said serialized bit stream, each of said plurality of HDSL channels comprising a fraction of a T1 or E1 channel; and  
       at said second site, a demultiplexer, which is coupled to said serial communication link and is operative to demultiplex said plurality of HDSL channels from said serialized bit stream;  
       said multiplexer and said demultiplexer each comprising a respective FIFO for clock rate adaptation.  
     
     
       8. An arrangement according to  claim 7 , further including a wireless communication device, coupled to said multiplexer and being operative to transmit said serialized bit stream over a wireless communication link to a wireless communication device associated with said second site. 
     
     
       9. An arrangement according to  claim 7 , wherein said prescribed HDSL-serialized communication protocol is effective to produce a sequence of bits that include framing bits for frame alignment, HDSL asynchronous channel bits for transporting HDSL embedded operations channel bits, bit-stuffing majority bits, a stuffing bit, an auxiliary signaling channel bit, and 1.544 Mbps T1 payload bits. 
     
     
       10. An arrangement according to  claim 7 , wherein said demultiplexer includes a framing pattern detector which is operative to detect a framing bit pattern in said serialized bit stream, and an output demultiplexer, which is operative to controllably derive said plurality of HDSL channels, and embedded operations channel bits from said serialized bit stream. 
     
     
       11. An arrangement according to  claim 10 , wherein said framing pattern detector is operative to adjust a timing attribute of said serialized bit stream in accordance with bit-stuffing majority bits and stuffing bits, so as to locate said framing bit pattern. 
     
     
       12. A communication mechanism for enabling high bit rate digital subscriber line (HDSL) communications to be conducted between a first site and a second site comprising: 
       an HDSL-serialized communication protocol, which is effective to combine a plurality of HDSL channels having a first bit rate into a serialized bit stream that includes control information that enables said second site to extract and reassemble each HDSL channel from said serialized bit stream, each of said plurality of HDSL channels comprising a fraction of a T1 or E1 channel; and  
       a communication processor, which is operative to multiplex said plurality of HDSL channels in accordance with said prescribed HDSL-serialized communication protocol, into said serialized bit stream having a second bit rate greater than twice that of said first bit rate, and containing said plurality of HDSL channels and said control information for transmission over said prescribed HDSL-serialized communication link to said second site;  
       said communication processor comprising a FIFO for clock rate adaptation.  
     
     
       13. A communication mechanism according to  claim 12 , further including a wireless communication device, which is operative to transmit said serialized bit stream containing said plurality of HDSL channels and said control information over a wireless communication link to a wireless communication device associated with said second site. 
     
     
       14. A communication mechanism according to  claim 12 , wherein said prescribed HDSL-serialized communication protocol is effective to generate a sequence of bits that include framing bits for frame alignment, HDSL asynchronous channel bits for transporting HDSL embedded operations channel bits, bit-stuffing majority bits, a stuffing bit, an auxiliary signaling channel bit, and 1.544 Mbps T1 payload bits. 
     
     
       15. A communication mechanism according to  claim 12 , wherein said second site includes a demultiplexer, which is operative to demultiplex said plurality of HDSL channels from said serialized bit stream. 
     
     
       16. A communication mechanism according to  claim 15 , further including a framing bit pattern detector coupled to said demultiplexer and being operative to detect a framing bit pattern in said serialized bit stream, and thereafter cause said demultiplexer to controllably derive said plurality of HDSL channels, and embedded operations channel bits from said serialized bit stream. 
     
     
       17. A communication mechanism according to  claim 16 , wherein framing bit pattern detector is operative to adjust a timing attribute of said serialized bit stream in accordance with bit-stuffing majority bits and stuffing bits, so as to locate said framing bit pattern.