Semiconductor integrated circuit having a voltage conversion circuit

Abstract

A semiconductor integrated circuit includes a first logic circuit to which a first power supply voltage is applied and which outputs a first signal, a first level conversion circuit to which the first power supply voltage and a second power supply voltage having an amplitude of second voltage level different from the first power supply voltage are supplied and which outputs a second signal, a second logic circuit to which the second power supply voltage is applied and which outputs a third signal, and a second level conversion circuit which is connected between the first and second logic circuits, to which the first and second power supply voltages are applied, and which level-converts the third signal of the second voltage level output from the second logic circuit to the first voltage level and outputs a fourth signal.

What is claimed is:  
     
       1. A semiconductor integrated circuit comprising: 
       a first logic circuit to which a first power supply voltage having a first amplitude is applied and which outputs a first signal having the first amplitude;  
       a power supply voltage detecting circuit to which the first power supply voltage and a second power supply voltage having a second amplitude larger than the first amplitude are applied and which outputs a detection signal representing level states of the first and second power supply voltages;  
       a level conversion circuit section to which the first and second power supply voltages are applied and which converts the first signal input from the first logic circuit into a second signal having the second amplitude and outputs a switching control signal on the basis of the detection signal;  
       an internal circuit which operates at the first power supply voltage; and  
       a switching circuit which is connected in series with the internal circuit across a power supply voltage terminals of the first power supply voltage and operates in accordance with the switching control signal from the level conversion circuit,  
       wherein when the detection signal output from the power supply voltage detecting circuit indicates voltage fluctuations of one of the first and second power supply voltages, the level conversion circuit section outputs a signal which opens the switching circuit.  
     
     
       2. The circuit according to  claim 1 , wherein the level conversion circuit section outputs the switching control signal upon fixing the signal to at least one of levels corresponding to the second amplitude. 
     
     
       3. The circuit according to  claim 2 , wherein the switching circuit includes a first switching element which is connected between a lower voltage terminal of the first power supply voltage and one terminal of the internal circuit, and a second switching element which is connected between a higher voltage terminal of the first power supply voltage and the other terminal of the internal circuit. 
     
     
       4. The circuit according to  claim 3 , wherein the level conversion circuit includes a first level conversion circuit which supplies a first output signal to the first switching element, and a second level conversion circuit which supplies a second output signal having an opposite polarity to the first output signal to the second switching element. 
     
     
       5. The circuit according to  claim 4 , wherein each of the first and second level conversion circuits has: 
       a full latch circuit comprising a first circuit including a first PMOS transistor and a first NMOS transistor which have current paths connected in series at a first node and gates connected to each other at a second node and are connected across power supply terminals of the second power supply voltage, a second circuit including a second PMOS transistor and a second NMOS transistor which have current paths connected in series at a second node and gates connected to each other at the first node and are connected across the power supply terminals of the second power supply voltage, a third NMOS transistor which has a gate to which the first signal is supplied, the third NMOS transistor being connected between the first node and one power supply terminal of the second power supply voltage (ground) and a fourth NMOS transistor which has a gate to which a signal having an opposite logic level to that of the first signal is supplied, the fourth NMOS transistor being connected between the second node and one power supply terminal of the second power supply voltage;  
       a fifth NMOS transistor which is connected between the first and second NMOS transistors of the full latch circuit and a lower voltage terminal of the second power supply voltage, and is controlled by the detection signal;  
       a sixth NMOS transistor which is connected between the second node and the lower voltage terminal of the second power supply voltage, and is controlled by the detection signal; and  
       a logic circuit element which receives the detection signal from the detecting circuit and the first power supply voltage and outputs, to the gate terminal of the sixth NMOS transistor, a signal having a logic level opposite to that from the fifth NMOS transistor.  
     
     
       6. The circuit according to  claim 5 , wherein each of the first and second level conversion circuits has an output terminal and a second logic circuit which is connected between the output terminal and the full latch circuit and to which the second power supply voltage is applied, and a seventh NMOS transistor which is connected between an output terminal of the second logic circuit and a lower voltage terminal of the second power supply voltage and controlled by the detection signal. 
     
     
       7. The circuit according to  claim 1 , wherein the internal circuit includes a sense amplifier connected to a memory array. 
     
     
       8. The circuit according to  claim 7 , further comprising an equalize control signal output circuit, and an equalizing element which is driven by an equalize control signal output from the equalize control signal output circuit and equalizes a potential on a power supply line in the sense amplifier. 
     
     
       9. The circuit according to  claim 8 , wherein the equalize control signal output circuit has a level conversion circuit which converts a first signal input from the first logic circuit into a second signal having a second amplitude, and output the equalize control signal having a level fixed to at least one of levels corresponding to the second amplitude when the detection signal output from the power supply voltage detecting circuit indicates a voltage fluctuations of one of the first and second power supply voltages. 
     
     
       10. The circuit according to  claim 9 , wherein the equalizing element is connected across power supply lines of the sense amplifier. 
     
     
       11. The circuit according to  claim 10 , wherein when the detection signal output from the power supply voltage detecting circuit indicates a change in level of at least one of the first and second power supply voltages, the level conversion circuit outputs, as an equalize signal, a signal fixed to a level at which the equalizing element is set in an unequalizing state. 
     
     
       12. The circuit according to  claim 1 , wherein the first logic circuit, the power supply voltage detecting circuit, and the level conversion circuit are formed on a signal semiconductor chip. 
     
     
       13. The circuit according to  claim 12 , wherein the semiconductor chip includes a DRAM macro.