US6816988B2ExpiredUtilityA1
Method and system for minimal-time bit-error-rate testing
Est. expiryAug 31, 2021(expired)· nominal 20-yr term from priority
Inventors:Lee A. Barford
G06F 11/221
71
PatentIndex Score
16
Cited by
13
References
60
Claims
Abstract
A bit-error rate is tested in a minimal necessary time period. A block of bits is measured and a cumulative number of bit errors is counted in parallel with calculation of a posterior cumulative distribution function. The posterior cumulative distribution function permits a determination to a desired probability whether or not the bit-error rate is less than a desired bit-error-rate limit. The measurement of blocks of bits and accumulation of bit errors relating thereto and calculation of the posterior cumulative distribution function and making of determinations based thereon continue in parallel until one of three events is detected. The three events are: 1) the bit-error rate is less than the desired bit-error rate limit to the desired probability; 2) the bit-error rate is greater than or equal to the desired bit-error rate limit to the desired probability; and 3) a maximal test time has been reached. Upon detection of any of these three conditions, the test is stopped.
Claims
exact text as granted — not AI-modifiedI claim:
1. A method of performing a bit-error-rate-test comprising the steps of:
(d) calculating a posterior cumulative distribution function (pcdf) of a bit-error rate based on a cumulative number of measured incorrect bits;
(e) determining whether pcdf is greater than or equal to a desired probability (C) that the bit-error rate is less than a bit-error-rate test limit (L);
(f) designating the test to have been passed and stopping the test in response to a determination that pcdf is greater than or equal to C;
(g) determining whether 1−pcdf is greater than or equal to C;
(h) designating the test to have been failed and stopping the test in response to a determination that 1−pcdf is greater than or equal to C;
(i) designating the test to have been failed and stopping the test in response to a determination that a test time has exceeded a maximal test time (T); and
(j) repeating steps (d)-(i) in response to a determination that pcdf is less than C and that 1−pcdf is less than C.
2. The method of claim 1 further comprising the steps of:
(a) measuring a plurality of bits;
(b) determining a cumulative number of measured incorrect bits; and
(c) in response to step b, repeating steps a and b.
3. The method of claim 2 wherein a number of the plurality of measured bits is set such that an amount of time for steps a and b to be performed is approximately equal to a worst-case time for steps d-i to be performed.
4. The method of claim 3 further comprising the steps of:
setting a test bit rate; and
determining the number of the measured plurality of bits by multiplying the test bit rate by the worst-case time.
5. The method of claim 3 wherein, following a first performance of steps a and b, steps a and b are performed in parallel with steps d-i.
6. The method of claim 2 further comprising the steps of:
setting L;
setting C;
setting an a priori mean (μ) of the bit-error rate;
setting an a priori standard deviation (σ) of the bit-error rate; and
setting T, wherein the setting steps are performed prior to step (a) being performed.
7. The method of claim 6 wherein the a priori mean and the a priori standard deviation are based on historical data or estimation.
8. The method of claim 6 wherein the a priori mean and the a priori standard deviation are set at 0.5 and 0.1, respectively.
9. The method of claim 6 further comprising the step of calculating values a and b, wherein: a = μ [ μ ( 1 - μ ) - σ 2 σ 2 ] ; b = ( 1 - μ ) [ μ ( 1 - μ ) - σ 2 σ 2 ] ; a n d
μ is the a priori mean and σ is the a priori standard deviation of the bit-error rate.
10. The method of claim 9 wherein the step of calculating the pcdf is performed using a purpose-written code.
11. The method of claim 10 wherein the purpose-written code is an incomplete beta function.
12. The method of claim 1 further comprising the step of calculating values a and b, wherein: a = μ [ μ ( 1 - μ ) - σ 2 σ 2 ] ; b = ( 1 - μ ) [ μ ( 1 - μ ) - σ 2 σ 2 ] ; a n d
μ is an a priori mean and σ is an a priori standard deviation of the bit-error rate.
13. The method of claim 12 wherein:
pcdf=∫ o L ρ R+a−1 (1−ρ) N−R+b−1 d ρ/Beta( R+a, N−R+b ).
14. The method of claim 13 wherein Beta (a,b) is a Gaussian Beta function.
15. The method of claim 13 wherein the step of calculating the pcdf is performed using a purpose-written code.
16. The method of claim 15 wherein the purpose-written code is an incomplete beta function.
17. The method of claim 1 wherein
pcdf=∫ o L ρ R+a−1 (1−ρ) N−R+b−1 d ρ/Beta( R+a, N−R+b ).
18. The method of claim 1 wherein the step of calculating the pcdf is performed using a purpose-written code.
19. The method of claim 18 wherein the purpose-written code is an incomplete beta function.
20. An article of manufacture for performing a bit-error-rate-test, the article of manufacture comprising:
at least one computer readable medium;
processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by at least one processor and thereby cause the at least one processor to operate as to:
(d) calculate a posterior cumulative distribution function (pcdf) of a bit-error rate based on a cumulative number of measured incorrect bits;
(e) determine whether pcdf is greater than or equal to a desired probability (C) that the bit-error rate is less than a bit-error-rate test limit (L);
(f) designate the test to have been passed and stop the test in response to a determination that pcdf is greater than or equal to C;
(g) determine whether 1−pcdf is greater than or equal to C;
(h) designate the test to have been failed and stop the test in response to a determination that 1−pcdf is greater than or equal to C;
(i) designate the test to have been failed and stop the test in response to a determination that a test time has exceeded a maximal test time (T); and
(j) repeat steps (d)-(i) in response to a determination that pcdf is less than C and that 1−pcdf is less than C.
21. The article of claim 20 further comprising processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by the at least one processor and thereby cause the at least one processor to operate as to:
(a) measure a plurality of bits;
(b) determine a cumulative number of measured incorrect bits; and
(c) in response to (b), repeat (a) and (b).
22. The article of claim 21 wherein a number of the plurality of measured bits is set such that an amount of time for (a) and (b) to be performed is approximately equal to a worst-case time for (d)-(i) to be performed.
23. The article of claim 22 further comprising processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by the at least one processor and thereby cause the at least one processor to operate as to:
set a test bit rate; and
determine the number of the measured plurality of bits by multiplying the test bit rate by the worst-case time.
24. The article of claim 22 wherein, following a first performance of (a) and (b), (a) and (b) are performed in parallel with (d)-(i).
25. The system of claim 21 further comprising processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by the at least one processor and thereby cause the at least one processor to operate as to:
set L;
set C;
set an a priori mean of the bit-error rate;
set an a priori standard deviation of the bit-error rate; and
set T, wherein L, C, the a priori mean, the a priori standard deviation, and T are set prior to (a) being performed.
26. The article of claim 25 wherein the a priori mean and the a priori standard deviation are based on historical data or estimation.
27. The article of claim 25 wherein the a priori mean and the a priori standard deviation are set at 0.5 and 0.1, respectively.
28. The article of claim 25 further comprising processor instructions contained on the at least one computer readable medium, processor instructions configured to be readable from the at least computer readable medium by the at least one processor and thereby cause the at least one processor to operate as to: a = μ [ μ ( 1 - μ ) - σ 2 σ 2 ] ; b = ( 1 - μ ) [ μ ( 1 - μ ) - σ 2 σ 2 ] ; a n d
μ is the a priori mean and σ is the a priori standard deviation of the bit-error rate.
29. The article of claim 28 wherein the calculation of the pcdf is performed using a purpose-written code.
30. The article of claim 29 wherein the purpose-written code is an incomplete beta function.
31. The article of claim 20 further comprising processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by the at least one processor and thereby cause the at least one processor to operate as to:
calculate values a and b, wherein: a = μ [ μ ( 1 - μ ) - σ 2 σ 2 ] ; b = ( 1 - μ ) [ μ ( 1 - μ ) - σ 2 σ 2 ] ; a n d
μ is an a priori mean and σ is an a priori standard deviation of the bit-error rate.
32. The article of claim 31 wherein
pcdf=∫ o L ρ R+a−1 (1−ρ) N−R+b−1 d ρ/Beta( R+a, N−R+b ).
33. The article of claim 32 wherein the calculation of the pcdf is performed using a purpose-written code.
34. The article of claim 33 wherein the purpose-written code is an incomplete beta function.
35. The article of claim 20 wherein
pcdf=∫ o L ρ R+a−1 (1−ρ) N−R+b−1 d ρ/Beta( R+a, N−R+b ).
36. The article of claim 20 wherein the calculation of the pcdf is performed using a purpose-written code.
37. The article of claim 36 wherein the purpose-written code is an incomplete beta function.
38. A system configured to perform a bit-error-rate-test, the system comprising:
a bit-sequence generator configured to input a bit sequence to a device under test (DUT);
delay generator interoperably connected to the bit-sequence generator;
a comparator interoperably connected to the DUT and to the delay generator, wherein the comparator is configured to compare an output of the delay generator to an output of the DUT;
a counter interoperably connected to the comparator, wherein the counter is configured to count an output of the comparator, the output being a cumulative number of incorrect bits; and
a control computer interoperably connected to the counter, wherein the computer is configured to:
(d) calculate a posterior cumulative distribution function (pcdf) of a bit-error rate based on the cumulative number of incorrect bits;
(e) determine whether pcdf is greater than or equal to a desired probability (C) that the bit-error rate is less than a bit-error-rate test limit (L);
(f) designate the test to have been passed and stop the test in response to a determination that pcdf is greater than or equal to C;
(g) determine whether 1−pcdf is greater than or equal to C;
(h) designate the test to have been failed and stop the test in response to a determination that 1−pcdf is greater than or equal to C;
(i) designate the test to have been failed and stop the test in response to a determination that a test time has exceeded a maximal test time (T); and
(j) repeat (d)-(i) in response to a determination that pcdf is less than C and that 1−pcdf is greater than C.
39. The system of claim 38 wherein the computer is further configured to:
(a) measure a plurality of bits;
(b) determine a cumulative number of measured incorrect bits; and
(c) in response to (b), repeat (a) and (b).
40. The system of claim 39 wherein a number of the plurality of measured bits is set such that an amount of time for (a) and (b) to be performed is approximately equal to a worst-case time for (d)-(i) to be performed.
41. The system of claim 40 wherein the computer is further configured to:
set a test bit rate; and
determine the number of the measured plurality of bits by multiplying the test bit rate by the worst-case time.
42. The system of claim 40 wherein, following a first performance of (a) and (b), (a) and (b) are performed in parallel with (d)-(i).
43. The system of claim 39 wherein the computer is further configured to:
set L;
set C;
set an a priori mean of the bit-error rate;
set an a priori standard deviation of the bit-error rate; and
set T, wherein L, C, the a priori mean, the a priori standard deviation, and T are set prior to (a) being performed.
44. The system of claim 43 wherein the a prior mean and the a priori standard deviation are based on historical data or estimation.
45. The system of claim 43 wherein the a priori mean and the a priori standard deviation are set at 0.5 and 0.1, respectively.
46. The system of claim 43 wherein the computer is further configured to calculate values a and b, wherein a = μ [ μ ( 1 - μ ) - σ 2 σ 2 ] ; b = ( 1 - μ ) [ μ ( 1 - μ ) - σ 2 σ 2 ] ; a n d
μ is the a priori mean and σ is the a priori standard deviation of the bit-error rate.
47. The system of claim 46 wherein the calculation of the pcdf is performed using a purpose-written code.
48. The system of claim 47 wherein the purpose-written code is an incomplete beta function.
49. The system of claim 38 wherein the computer is further configured to calculate values a and b, wherein: a = μ [ μ ( 1 - μ ) - σ 2 σ 2 ] ; b = ( 1 - μ ) [ μ ( 1 - μ ) - σ 2 σ 2 ] ; a n d
μ is an a priori mean and σ is an a priori standard deviation of the bit-error rate.
50. The system of claim 49 wherein
pcdf=∫ o L ρ R+a−1 (1−ρ) N−R+b−1 d ρ/Beta( R+a, N−R+b ).
51. The system of claim 50 wherein Beta (a,b) is a Gaussian Beta function.
52. The system of claim 50 wherein the calculation of the pcdf is performed using a purpose-written code.
53. The system of claim 52 wherein the purpose-written code is an incomplete beta function.
54. The system of claim 38 wherein
pcdf=∫ o L ρ R+a−1 (1−ρ) N−R+b−1 d ρ/Beta( R+a, N−R+b ).
55. The system of claim 38 wherein the calculation of the pcdf is performed using a purpose-written code.
56. The system of claim 55 wherein the purpose-written code is an incomplete beta function.
57. A method, comprising:
(i) providing a test sequence to a device under test (DUT);
(ii) recording errors of said DUT that occur in response to said test sequence;
(iii) calculating a cumulative observed error rate;
(iv) calculating a first cumulative probability that an error rate of said DUT is less than a threshold value using said cumulative observed error rate, an a priori mean and an a priori standard deviation;
(v) calculating a second cumulative probability that an error rate of said DUT is greater than a threshold value; and
(vi) when said first and second cumulative probabilities do not exceed a predetermined confidence value, repeating steps (i)-(v);
wherein steps (i)-(vi) are performed by a bit-error rate testing device.
58. The method of claim 57 further comprising:
when one of said first and second cumulative probabilities exceed a predetermined confidence value, terminating testing of said DUT.
59. The method of claim 57 further comprising:
when a test time exceeds a predetermined amount of time without said first and second cumulative probabilities exceeding a predetermined confidence value, terminating said testing of said DUT and identifying said DUT as a failing device.
60. The method of claim 57 wherein said calculating said first cumulative probability comprises integrating a distribution function.Cited by (0)
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