Low power buffer implementation

Abstract

A lower current input buffer is used for waking up a plurality of higher-current buffers. The lower current buffer monitors a wake-up signal and, when present, enables the higher current buffers. A higher current buffer is used to detect the sleep mode and disable the higher current buffers. A delay circuit may be used to balance the propagation delay through the circuit.

What is claimed is:  
     
       1. A buffer circuit for detecting a power up condition, comprising: 
       a lower power buffer, for detecting a power up condition;  
       a first higher power buffer, for detecting a power down condition; and  
       a plurality of second higher power buffers, each connected to buffer respective signal lines;  
       wherein said lower power buffer enables said plurality of second higher power buffers when a power up condition is detected, and said first higher power buffer disables said plurality of second higher power buffers when a power down condition is detected.  
     
     
       2. The buffer circuit of  claim 1 , wherein said first and second higher power buffers are differential buffers. 
     
     
       3. The buffer circuit of  claim 1 , wherein said lower power buffer is a CMOS buffer. 
     
     
       4. The buffer circuit  claim 1 , wherein said lower power buffer is a CMOS inverter. 
     
     
       5. The buffer circuit of  claim 1 , wherein said lower power buffer detects a transition in a clock enable signal indicating power up. 
     
     
       6. The buffer circuit of  claim 5 , wherein said first higher power buffer detects a transition of a clock enable signal indicating power down. 
     
     
       7. The buffer circuit of  claim 5 , wherein said lower and first higher power buffer for detecting power up and power down conditions are provided within logic circuitry which transforms an external clock enable signal into an internal enable/disable signal for enabling/disabling said plurality of second higher power buffers. 
     
     
       8. The buffer circuit of  claim 7 , wherein said logic circuitry further comprises a selectable delay circuit to equalize buffer transition time, and said logic circuitry selectively introduces said delay when said lower power buffer is operable. 
     
     
       9. The buffer circuit of  claim 8 , wherein said logic circuitry further comprises an NMOS transistor operated by a signal derived from said external clock enable signal for stabilizing said internal clock enable/disable signal during a power down condition. 
     
     
       10. The buffer circuit of  claim 8 , wherein said logic circuitry verifies the authenticity of said internal clock enable/disable signal. 
     
     
       11. The buffer circuit of  claim 1 , wherein said respective signal lines comprise address lines. 
     
     
       12. The buffer circuit of  claim 1 , wherein said respective signal lines comprise command lines. 
     
     
       13. The buffer circuit of  claim 1 , wherein said respective signal lines comprise clock lines. 
     
     
       14. The buffer circuit of  claim 1 , wherein said respective signal lines comprise data lines. 
     
     
       15. The buffer circuit of  claim 7  wherein said lower power buffer and said first higher power buffer monitor an enable input signal, and said logic circuitry has a first setup time requirement for a power up condition, and a second different setup time requirement for a power down signal. 
     
     
       16. A method of detecting the state of a clock enable signal, comprising: detecting a power up condition with a lower power buffer; detecting a power down condition with a first higher power buffer, 
       enabling a plurality of second higher power buffers, each connected to buffer respective signal lines, upon detection of said power up condition by said lower power buffer; and  
       disabling said plurality of second higher power buffers when a power down condition is detected by said first higher power buffer.  
     
     
       17. The method of  claim 16 , wherein said lower power buffer is a CMOS buffer. 
     
     
       18. The method of  claim 16 , wherein said lower power buffer is a CMOS inverter. 
     
     
       19. The method of  claim 16 , wherein said detecting a power down condition is accomplished by a higher power buffer. 
     
     
       20. The method of  claim 18 , wherein said lower power buffer detects a transition in a clock enable signal indicating power up. 
     
     
       21. The method of  claim 17 , further comprising: 
       transforming an external clock enable signal into an internal clock enable/disable signal suitable for connecting to said plurality of second higher power buffers.  
     
     
       22. The method of  claim 21 , further comprising: 
       verifying the authenticity of said internal clock enable signal.  
     
     
       23. The method of  claim 16 , wherein said signal lines comprise address lines. 
     
     
       24. The method of  claim 16 , wherein said signal lines comprise command lines. 
     
     
       25. The method of  claim 16 , wherein said signal lines comprise clock lines. 
     
     
       26. The method of  claim 16 , wherein said signal lines comprise data lines. 
     
     
       27. A circuit for detecting a power up or power down condition, comprising: 
       a lower power buffer, for detecting a power up condition;  
       first higher power buffer, for detecting a power down condition  
       a plurality of second higher power buffers, each connected to respective signal lines;  
       wherein said lower power buffer enables said plurality of second higher power buffers when a power up condition is detected, and said first higher power buffer disables said plurality of second higher power buffers when a power down condition is detected; and  
       logic circuitry for transforming an external clock enable signal into an internal enable/disable signal suitable for said plurality of second higher power buffers, said logic circuitry further comprising:  
       a delay circuit for delaying the propagation of a signal from said lower power buffer as it passes through said logic circuit without delaying the propagation of a signal from said first higher power buffer.  
     
     
       28. The detection circuit of  claim 27 , wherein said first and second higher power buffers are differential buffers. 
     
     
       29. The detection circuit of  claim 27 , wherein said lower power buffer is a CMOS buffer. 
     
     
       30. The detection circuit of  claim 27 , wherein said lower power buffer is a CMOS inverter. 
     
     
       31. The detection circuit of  claim 27 , wherein said lower power buffer detects a transition in a clock enable signal indicating power up. 
     
     
       32. The detection circuit of  claim 27 , wherein said first higher power buffer detects a transition of a clock enable signal indicating power down. 
     
     
       33. The detection circuit of  claim 27 , wherein said logic circuitry verifies the authenticity of said internal clock enable/disable signal. 
     
     
       34. The detection circuit of  claim 27 , wherein said respective signal lines comprise address lines. 
     
     
       35. The detection circuit of  claim 27 , wherein said respective signal lines comprise command lines. 
     
     
       36. The detection circuit of  claim 27 , wherein said respective signal lines comprise clock lines. 
     
     
       37. The detection circuit of  claim 27 , wherein said respective signal lines comprise data lines. 
     
     
       38. The detection circuit of  claim 27 , wherein said lower power buffer and said higher power buffer monitor an enable input signal, and said logic circuitry has a first setup time requirement for a power up condition, and a second different setup time requirement for a power down signal. 
     
     
       39. A processor circuit, comprising: 
       a processor; and  
       a memory circuit for exchanging data with said processor;  
       at least one of said processor and memory circuit comprising a buffer circuit, said buffer circuit further comprising:  
       a lower power buffer, for detecting a power up condition;  
       a first higher power buffer, for detecting a power down condition;  
       a plurality of second higher power buffers, each connected to buffer respective signal lines;  
       wherein said lower power buffer enables said plurality of second higher power buffers when a power up condition is detected, and said first higher power buffer disables said plurality of second higher power buffers when a power down condition is detected.  
     
     
       40. The buffer circuit of  claim 39 , wherein said first and second higher power buffers are differential buffers. 
     
     
       41. The buffer circuit of  claim 39 , wherein said lower power buffer is a CMOS buffer. 
     
     
       42. The buffer circuit  claim 39 , wherein said lower power buffer is a CMOS inverter. 
     
     
       43. The buffer circuit of  claim 39 , wherein said lower power buffer detects a transition in a clock enable signal indicating power up. 
     
     
       44. The buffer circuit of  claim 39 , wherein said first higher power buffer detects a transition of a clock enable signal indicating power down. 
     
     
       45. The buffer circuit of  claim 39 , wherein said lower and first higher power buffer for detecting power up and power down conditions are provided within logic circuitry which transforms an external clock enable signal into an internal enable/disable signal for enabling/disabling said plurality of second higher power buffers. 
     
     
       46. The buffer circuit of  claim 45 , wherein said logic circuitry further comprises a selectable delay circuit to equalize buffer transition time, and said logic circuitry selectively introduces said delay when said lower power buffer is operable. 
     
     
       47. The buffer circuit of  claim 45 , wherein said logic circuitry further comprises an NMOS transistor operated by a signal derived from said external clock enable signal for stabilizing said internal clock enable/disable signal during a power down condition. 
     
     
       48. The buffer circuit of  claim 45 , wherein said logic circuitry verifies the authenticity of said internal clock enable/disable signal. 
     
     
       49. The buffer circuit of  claim 39 , wherein said respective signal lines comprise address lines. 
     
     
       50. The buffer circuit of  claim 39 , wherein said respective signal lines comprise command lines. 
     
     
       51. The buffer circuit of  claim 39 , wherein said respective signal lines comprise clock lines. 
     
     
       52. The buffer circuit of  claim 39 , wherein said respective signal lines comprise data lines. 
     
     
       53. The buffer circuit of  claim 50 , wherein said lower power buffer and said first higher power buffer monitor an enable input signal, and said logic circuitry has a first setup time requirement for a power up condition, and a second different setup time requirement for a power down signal.