CMOS comparator output stage and method

Abstract

A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit ( 6 ) producing a first delayed signal, (V 7 ) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit ( 4 ) producing a second delayed signal (V 5 ) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

What is claimed is:  
     
       1. A CMOS circuit including a P-channel pull-up transistor and an N-channel pull-down transistor, comprising: 
       (a) a P-channel first transistor having a source coupled to a first supply voltage and a gate coupled to a first input terminal for receiving a first input current, and an N-channel second transistor having a source coupled to a second supply voltage and a gate coupled to a second input terminal for receiving a second input current;  
       (b) a P-channel third transistor having a source coupled to the first supply voltage, a gate coupled to the first input terminal, and a drain coupled to a gate of the pull-up transistor, and an N-channel fourth transistor having a source coupled to the second supply voltage and a gate coupled to the second input terminal;  
       (c) a first feedback circuit having an input coupled to the gate of the pull-up transistor and an output coupled to a gate of a P-channel fifth transistor having a source coupled to a drain of the P-channel first transistor a drain coupled to a gate of the pull-down transistor and a drain of the N-channel second transistor, and a second feedback circuit having an input coupled to the gate of the pull-down transistor and an output coupled to a gate of an N-channel sixth transistor having a source coupled to a drain of the N-channel fourth transistor and a drain coupled to the gate of the pull-up transistor;  
       (d) the first feedback circuit producing a first delayed signal on the gate of the P-channel fifth transistor which causes the P-channel fifth transistor to turn on the pull-down transistor a first predetermined amount of time after the pull-up transistor is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor and the pull-down transistor, the second feedback circuit producing a second delayed signal on the gate of the N-channel sixth transistor which causes the N-channel sixth transistor to turn on the pull-up transistor a second predetermined amount of time after the pull-down transistor is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor and the pull-down transistor.  
     
     
       2. The CMOS circuit of  claim 1  including a class AB control circuit coupled between the first and second input terminals. 
     
     
       3. The CMOS circuit of  claim 1  wherein the first feedback circuit includes a first CMOS inverter, a first current source coupled between the first CMOS inverter and the second supply voltage, an input coupled to the gate of the pull-up transistor, and an output coupled to the gate of the P-channel fifth transistor. 
     
     
       4. The CMOS circuit of  claim 1  wherein the P-channel fifth transistor is included in the first feedback circuit. 
     
     
       5. The CMOS circuit of  claim 3  wherein the first CMOS inverter includes a P-channel seventh transistor having a source coupled to the first supply voltage and an N-channel eighth transistor having a drain coupled to the drain of the P-channel seventh transistor and a source coupled to the first current source. 
     
     
       6. The CMOS circuit of  claim 3  wherein the second feedback circuit includes a second CMOS inverter, a second current source coupled between the second CMOS inverter and the first supply voltage, an input coupled to the gate of the pull-down transistor, and an output coupled to the gate of the N-channel sixth transistor. 
     
     
       7. The CMOS circuit of  claim 6  wherein the N-channel sixth transistor is included in the second feedback circuit. 
     
     
       8. The CMOS circuit of  claim 6  wherein the second CMOS inverter includes an N-channel ninth transistor having a source coupled to the second supply voltage and a P-channel tenth transistor having a drain coupled to the drain of the N-channel ninth transistor and a source coupled to the second current source. 
     
     
       9. The CMOS circuit of  claim 1  wherein the first and second input currents are produced by a folded cascode stage of an input stage of a CMOS comparator circuit. 
     
     
       10. The CMOS circuit of  claim 9  including a class AB control circuit coupled between the first and second input terminals. 
     
     
       11. The CMOS circuit of  claim 9  wherein the input stage of the CMOS comparator circuit is a differential input stage, and wherein the folded cascode stage is a differential folded cascode stage of the differential input stage of the CMOS comparator circuit. 
     
     
       12. A method of preventing shoot-through current in a CMOS circuit including a P-channel pull-up transistor and an N-channel pull-down transistor, the method comprising: 
       (a) applying a first input current to a gate of a P-channel first transistor having a source coupled to a first supply voltage and to a gate of a P-channel third transistor having a source coupled to the first supply voltage and a drain coupled to a gate of the pull-up transistor, and applying a second input current to a gate of an N-channel second transistor having a source coupled to a second supply voltage and a gate of an N-channel fourth transistor having a source coupled to the second supply voltage;  
       (b) producing a first delayed signal on a gate of a P-channel fifth transistor by means of a first feedback circuit having an input coupled to the gate of the pull-up transistor, a source of the P-channel fifth transitor is coupled to a drain of the P-channel first transistor and a drain coupled to a gate of the pull-down transistor and a drain of the N-channel second transistor, and an output coupled to a gate of the fifth transistor to cause the P-channel fifth transistor to turn on the pull-down transistor a first predetermined amount of time after the pull-up transistor is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor and the pull-down transistor; and  
       (c) producing a second delayed signal on a gate of a sixth transistor by means of a second feedback circuit having an input coupled to the gate of the pull-down transistor, a source of the sixth transitor is coupled to source a drain of the N-channel fourth transistor and a drain coupled to the gate of the pull-up transistor, and an output coupled to the gate of the sixth transistor to cause the sixth transistor to turn on the pull-up transistor a second predetermined amount of time after the pull-down transistor is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor and the pull-down transistor.  
     
     
       13. A CMOS circuit including a P-channel pull-up transistor and an N-channel pull-down transistor, comprising: 
       (a) a P-channel first transistor having a source coupled to a first supply voltage and a gate coupled to an input terminal for receiving an input voltage, and an N-channel second transistor having a source coupled to a second supply voltage and a gate coupled to the input terminal;  
       (b) a P-channel third transistor having a source coupled to the first supply voltage, a gate coupled to the input terminal, and a drain coupled to a gate of the pull-up transistor, and an N-channel fourth transistor having a source coupled to the second supply voltage and a gate coupled to the input terminal;  
       (c) a first feedback circuit having an input coupled to the gate of the pull-up transistor and an output coupled to a gate of a P-channel fifth transistor having a source coupled to a drain of the first transistor and a drain coupled to a gate of the pull-down transistor and a drain of the N-channel second transistor, and a second feedback circuit having an input coupled to the gate of the pull-down transistor and an output coupled to a gate of an N-channel sixth transistor having a source coupled to a drain of the fourth transistor and a drain coupled to the gate of the pull-up transistor;  
       (d) the first feedback circuit producing a first delayed signal on the gate of the P-channel fifth transistor which causes the P-channel fifth transistor to turn on the pull-down transistor a first predetermined amount of time after the pull-up transistor is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor and the pull-down transistor, the second feedback circuit producing a second delayed signal on the gate of the sixth transistor which causes the sixth transistor to turn on the pull-up transistor a second predetermined amount of time after the pull-down transistor is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor and the pull-down transistor.