Power reduction by stage in integrated circuit

Abstract

An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.

What is claimed is:  
     
       1. An integrated circuit comprising: 
       a plurality of paths including a critical path for a particular cycle, the critical path including a plurality of stages;  
       means, within the integrated circuit, for dynamically changing a voltage level of least one stage for the particular cycle; and  
       means within the integrated circuit for determining a voltage switch latency period for each stage;  
       wherein the means for changing the voltage level changes the voltage level sufficiently prior to the particular cycle to accommodate the voltage switch latency period of a respective stage.  
     
     
       2. The integrated circuit of  claim 1 , wherein the means for dynamically changing the voltage level includes: 
       means for determining a voltage level required for each stage for the particular cycle; and  
       means for changing the voltage level of the at least one stage for the particular cycle.  
     
     
       3. The integrated circuit of  claim 2 , wherein the means for determining includes means for analyzing an operation code and determining a voltage level required for each stage. 
     
     
       4. The integrated circuit of  claim 2 , wherein, the means for changing transmits a voltage level control as a bit token for the at least one stage with a data flow along the critical path. 
     
     
       5. The integrated circuit of  claim 2 , wherein each stage includes means for deciphering the voltage level control. 
     
     
       6. The integrated circuit of  claim 5 , wherein the means for deciphering includes control circuit at each stage, each control circuit having: 
       a control input coupled to the means for changing;  
       a first transistor coupled to the control input and to a first voltage level;  
       a second transistor coupled to the control input via an inverter and to a second voltage level;  
       an output coupled to each of the first and second transistors and to a functional element of the respective stage;  
       wherein the control input determines which of the first and second voltage levels is delivered to the output; and  
       wherein the first voltage level is different than the second voltage level.  
     
     
       7. A method of reducing power consumption of an integrated circuit comprising: 
       transmitting data along one of a plurality of paths based on a particular operation to be executed, each path including a plurality of stages that operate on the data;  
       changing a voltage level of at least one stage; and  
       determining a voltage switch latency period for each stage.  
     
     
       8. The method of  claim 7 , further comprising the step of determining a required voltage level for each stage. 
     
     
       9. The method of  claim 8 , wherein the step of determining includes analyzing an operation code to determine a voltage level required of each stage. 
     
     
       10. The method of  claim 7 , wherein the step of changing the voltage level includes transmitting the voltage level sufficiently prior to the particular cycle to accommodate the voltage switch latency period of a respective stage. 
     
     
       11. The method of  claim 7 , wherein the step of changing includes transmitting a voltage level control as a bit token for the at least one stage with a data flow along the path. 
     
     
       12. A system for reducing power consumption of an integrated circuit, the system comprising: 
       means, within the integrated circuit, for determining a voltage level required for each stage on a path used for a particular cycle;  
       means, within the integrated circuit, for changing the voltage level of at least one stage on the path; and  
       means, within the integrated circuit for determining a voltage switch latency period for each stage;  
       wherein the means for changing the voltage level changes the voltage level sufficiently prior to the particular cycle to accommodate the voltage switch latency period of a respective stage.  
     
     
       13. The system of  claim 12 , wherein the means for determining includes means for analyzing an operation code and determining a voltage level required for each stage. 
     
     
       14. The system of  claim 12 , wherein each stage includes means for deciphering a voltage level control from the means for changing. 
     
     
       15. The system of  claim 14 , wherein the means for deciphering includes a control circuit at each stage, each control circuit having: 
       a control input coupled to the means for changing;  
       a first transistor coupled to the control input and to a first voltage level;  
       a second transistor coupled to the control input via an inverter and to a second voltage level;  
       an output coupled to each of the first and second transistors and to a functional element of the respective stage;  
       wherein the control input determines which of the first and second voltage levels is delivered to the output; and  
       wherein the first voltage level is different than the second voltage level.  
     
     
       16. The system of  claim 12 , wherein the means for changing the voltage level transmits a voltage level control for at least one stage as a bit token with a data flow along the path. 
     
     
       17. The system of  claim 12 , wherein the path is one of a plurality of paths used for the particular cycle.