P
US6828857B2ExpiredUtilityPatentIndex 93

High gain, high bandwidth CMOS transimpedance amplifier

Assignee: INTEL CORPPriority: Dec 11, 2002Filed: Dec 11, 2002Granted: Dec 7, 2004
Est. expiryDec 11, 2022(expired)· nominal 20-yr term from priority
Inventors:PAILLET FABRICEKARNIK TANAY
H03F 3/3022H03F 3/345H03F 1/342
93
PatentIndex Score
36
Cited by
4
References
15
Claims

Abstract

A three-stage transimpedance amplifier, where the first stage is a shunt-shunt feedback amplifier, the second stage is a simple voltage amplifier, and the third stage is a shunt-shunt feedback amplifier. The third stage comprises a pMOSFET serially connected with a nMOSFET, where their gates are connected together and to the output port of the second stage, and comprises a feedback pMOSFET or resistor to provide negative feedback from the drains of the pMOSFET and nMOSFET to the output port of the second stage.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. An amplifier comprising: 
       a first shunt-shunt feedback stage;  
       a voltage amplifier stage coupled to the first shunt-shunt feedback stage; and  
       a second shunt-shunt feedback stage coupled to the voltage amplifier stage.  
     
     
       2. The amplifier as set forth in  claim 1 , wherein the second shunt-shunt feedback stage comprises: 
       a pMOSFET comprising a drain and a gate;  
       a nMOSFET comprising a gate, and comprising a drain connected to-the drain of the pMOSFET; and  
       a feedback element coupling the drains of the pMOSFET to the gates of the pMOSFET and the nMOSFET.  
     
     
       3. The amplifier as set forth in  claim 2 , wherein the gates of the pMOSFET and the nMOSFET are connected to each other. 
     
     
       4. The amplifier as set forth in  claim 3 , wherein the first shunt-shunt feedback stage comprises: 
       a pMOSFET comprising a drain;  
       a nMOSFET comprising a drain connected to the drain of the pMOSFET of the first shunt-shunt feedback stage; and  
       a feedback element coupling the drain of the nMOSFET of the first shunt-shunt feedback stage to the gate of the nMOSFET of the first shunt-shunt feedback stage.  
     
     
       5. The amplifier as set forth in  claim 4 , wherein the voltage amplifier stage comprises: 
       a pMOSFET comprising a drain; and  
       a nMOSFET comprising a drain connected to the drain of the pMOSFET of the voltage amplifier stage, and comprising a gate connected to the drain of the nMOSFET of the first shunt-shunt feedback stage.  
     
     
       6. The amplifier as set forth in  claim 5 , wherein the feedback element of the second shunt-shunt feedback stage comprises a feedback pMOSFET comprising first and second source/drain terminals connected, respectively, to the drain and the gate of the nMOSFET of the second shunt-shunt feedback stage. 
     
     
       7. The amplifier as set forth in  claim 2 , wherein the feedback element of the second shunt-shunt feedback stage comprises a feedback pMOSFET comprising first and second source/drain terminals connected, respectively, to the drain and the gate of the nMOSFET of the second shunt-shunt feedback stage. 
     
     
       8. The amplifier as set forth in  claim 5 , wherein the feedback element of the second shunt-shunt feedback stage comprises a feedback resistor comprising first and second terminals connected, respectively, to the drain and the gate of the nMOSFET of the second shunt-shunt feedback stage. 
     
     
       9. The amplifier as set forth in  claim 2 , wherein the feedback element of the second shunt-shunt feedback stage comprises a feedback resistor comprising first and second terminals connected, respectively, to the drain and the gate of the n-MOSFET of the second shunt-shunt feedback stage. 
     
     
       10. A computer system comprising: 
       a photodetector comprising an output port; and  
       an amplifier comprising an input port coupled to the output port of the photodetector, the amplifier comprising:  
       a first shunt-shunt feedback stage;  
       a voltage amplifier stage coupled to the first shunt-shunt feedback stage; and  
       a second shunt-shunt feedback stage coupled to the voltage amplifier stage.  
     
     
       11. The computer system as set forth in  claim 10 , wherein the second shunt-shunt feedback stage comprises: 
       a pMOSFET comprising a drain and a gate;  
       a nMOSFET comprising a gate, and comprising a drain connected to the drain of the pMOSFET; and  
       a feedback element coupling the drains of the pMOSFET to the gates of the pMOSFET and the nMOSFET.  
     
     
       12. The computer system as set forth in  claim 11 , wherein the gates of the pMOSFET and the nMOSFET are connected to each other. 
     
     
       13. An transimpedance amplifier comprising: 
       a first stage comprising  
       a common-source amplifier comprising a transistor, the transistor comprising a gate and a drain; and  
       a feedback element coupling the drain of the transistor to the gate of the transistor to provide negative feedback;  
       a second stage comprising  
       a common-source amplifier comprising a transistor, the transistor in the second stage comprising a gate connected to the drain of the transistor in the first stage and comprising a drain; and  
       a third stage comprising:  
       a nMOSFET comprising a drain and comprising a gate connected to the drain of the transistor in the second stage;  
       a pMOSFET comprising a gate and a drain connected, respectively, to the gate and to the drain of the nMOSFET; and  
       a feedback element coupling the drain of the nMOSFET to the gate of the nMOSFET.  
     
     
       14. The transimpedance amplifier as set forth in  claim 13 , wherein the feedback element comprises a resistor comprising a first terminal and a second terminal connected, respectively, to the drain and to the gate of the nMOSFET. 
     
     
       15. The transimpedance amplifier as set forth in  claim 13 , wherein the feedback element comprises a pMOSFET comprising a first source/drain and a second source/drain connected, respectively, to the drain and to the gate of the nMOSFET.

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