Time sequentially scanned display

Abstract

A time sequentially scanned display comprises a matrix 20 of picture elements 21 . Each of the picture elements comprises a display element 9 , for instance of liquid crystal type. An addressable latch 3 has a plurality of storage locations which may be selectively updated in response to an address supplied to an address input. A multiplexer 7 supplies image data from any one of the storage locations at a time to the display element 9 . The multiplexer has an address input for selecting which of the storage locations of the latch 3 supplies image data to the display element 9 . In some of the embodiments, the address inputs are connected together and addressed by the outputs of a single counter 11 whereas, in other embodiments, the address inputs of the latch 3 and the multiplexer 7 are addressed independently, for instance by two counters 11 a and 11 b . Such an arrangement permits various types of asynchronous operation between addressing and displaying data.

What is claimed is:  
     
       1. A time sequentially scanned display comprising a matrix of picture elements, each of which comprises a display element, an addressable latch having a plurality of storage locations and a first address input for selecting any one of the storage locations for storing image data, and a multiplexer for supplying image data from any one of the storage locations at a time to the display element, the multiplexer having a second address input for selecting which of the storage locations supplies image data to the display element, 
       wherein the addressable latch comprises a demultiplexer and a latch, the demultiplexer for supplying image data to the latch.  
     
     
       2. A display according to  claim 1 , in which each of the picture elements comprises an addressing arrangement for supplying addresses to the first and second address inputs. 
     
     
       3. A display according to  claim 2 , in which each of the addressing arrangements comprises a counter whose output is connected to the first and second addressing inputs so that the storage locations are selected for storing image data in a first predetermined sequence and for supplying image data to the display element in a second predetermined sequence which is identical to but one step out of phase with the first predetermined sequence. 
     
     
       4. A display according to  claim 3 , in which the counter has a clock input connected to the output of a transfer signal detector whose input is connected to a scan or data electrode of the matrix. 
     
     
       5. A display according to  claim 3 , in which the counter is a modulo counter having a modulo control input provided with a latching arrangement. 
     
     
       6. A display according to  claim 5 , in which the latching arrangement has data inputs connected to at least some outputs of the storage locations. 
     
     
       7. A display according to  claim 6 , in which the latching arrangement is arranged to be enabled by an output of a decoder. 
     
     
       8. A display according to  claim 7 , in which the counter has a clock input connected to the output of a transfer signal detector whose input is connected to a scan or data electrode of the matrix, 
       in which the decoder comprises a counter having a clock input connected to the output of the transfer signal detector and a reset input connected to a or the scan electrode.  
     
     
       9. A display according to  claim 2 , in which each of the addressing arrangements comprises first and second counters whose outputs are connected to the first and second address inputs, respectively. 
     
     
       10. A display according to  claim 9 , in which the first counter has a clock input connected to a scan electrode of the matrix. 
     
     
       11. A display according to  claim 10 , in which the first and second counters are modulo counters having modulo control inputs provided with a latching arrangement. 
     
     
       12. A display according to  claim 9 , in which the second counter has a clock input connected to the output of a transfer signal detector whose input is connected to a scan electrode or a data electrode of the matrix. 
     
     
       13. A display according to  claim 12 , in which the first and second counters are modulo counters having modulo control inputs provided with a latching arrangement. 
     
     
       14. A display according to  claim 9 , in which the addressing arrangement comprises a reset arrangement for resetting the first and second counters when power is applied to the display. 
     
     
       15. A display according to  claim 9 , in which the first and second counters are modulo counters having modulo control inputs provided with a latching arrangement. 
     
     
       16. A display according to  claim 15 , in which the latching arrangement has data inputs connected to at least some outputs of the storage locations. 
     
     
       17. A display according to  claim 16 , in which the latching arrangement is arranged to be enabled by an output of a decoder. 
     
     
       18. A display according to  claim 17 , in which the second counter has a clock input connected to the output of a transfer signal detector whose input is connected to a or the scan electrode or a data electrode of the matrix, 
       in which the decoder comprises a counter having a reset input connected to the output of the transfer signal detector and a clock input connected to a scan electrode.  
     
     
       19. A display according to  claim 1 , in which each addressable latch comprises an analog addressable latch. 
     
     
       20. A display according to  claim 1 , in which each addressable latch comprises a latch having the plurality of storage locations and a demultiplexer for selectively supplying the image data to any one of the storage locations. 
     
     
       21. A display according to  claim 1 , in which each addressable latch has a clock input connected to a scan electrode and a data input connected to a data electrode. 
     
     
       22. A display according to  claim 1 , in which each addressable latch has storage locations for red, green and blue image data. 
     
     
       23. A display according to  claim 1 , in which each addressable latch has storage locations for red, green, blue and intensity image data. 
     
     
       24. A display according to  claim 1 , in which each addressable latch has storage locations for red, green and blue image data for two image fields or frames. 
     
     
       25. A display according to  claim 1 , in which each addressable latch has storage locations for red, green, blue, white and/or black image data. 
     
     
       26. A display according to  claim 25 , in which the storage locations for the white and/or black image data are hard-wired to receive voltage levels which are not addressable. 
     
     
       27. A display according to  claim 1 , comprising a multi-colour backlight and a backlight controller. 
     
     
       28. A display according to  claim 1 , in which each display element comprises a liquid crystal picture element. 
     
     
       29. A display according to  claim 28 , in which each display element is of reflective type. 
     
     
       30. A display according to  claim 29 , in which the addressable latches and the multiplexers are embodied as crystalline silicon or poly-silicon. 
     
     
       31. A display according to  claim 29 , in which the addressable latches and the multiplexers are disposed behind the reflective display elements. 
     
     
       32. A method of operating a display according to  claim 1 , comprising supplying image data to the picture elements in first sets of time-sequential addressing phases with each first set constituting a frame of image data and displaying the image data in second sets of time-sequential display phases with each second set constituting a frame of image data, the number of display phases in each of the second sets being greater than or equal to the number of addressing phases in each of the first sets. 
     
     
       33. A method according to  claim 32 , in which the addressing phases of each of the first sets comprise different component colour addressing phases, the display phases of each of the second sets comprise component colour display phases, and at least one component colour display phase is repeated in each of the second sets. 
     
     
       34. A method according to  claim 33 , in which a green display phase is repeated in each of the second sets. 
     
     
       35. A method according to  claim 33 , in which the image data supplied during at least some of the addressing phases comprises or contains control data for controlling an aspect of pixel operation. 
     
     
       36. A method according to  claim 32 , in which the number of display phases in each of the second sets is an integer multiple of the number of addressing phases in each of the first sets. 
     
     
       37. A method according to  claim 36 , in which the addressing phases of each of the first sets comprise different component colour addressing phases, the display phases of each of the second sets comprise component colour display phases, and at least one component colour display phase is repeated in each of the second sets, 
       in which all of the colour component display phases are repeated the same number of times in each of the second sets.  
     
     
       38. A method according to claims  32 , in which each addressable latch has storage locations for red, green, blue, white and/or black image data, 
       in which white and/or black addressing phases occur in only some of the first sets.  
     
     
       39. A method according to any one of claims  32 , in which each display element comprises a liquid crystal picture element, 
       in which the maximum electro-optic response time of the liquid crystal picture elements is substantially equal to or less than the duration of each of the display phases.  
     
     
       40. A method according to  claim 39 , in which the image data supplied during at least some of the addressing phases comprises or contains control data for controlling an aspect of pixel operation. 
     
     
       41. A method according to  claim 40 , in which the counter is a modulo counter having a modulo control input provided with a latching arrangement, 
       in which the aspect of pixel operation comprises the modulo of each modulo counter.  
     
     
       42. A method according to  claim 40 , in which the first and second counters are modulo counters having modulo control inputs provided with a latching arrangement, 
       in which the aspect of pixel operation comprises the modulo of each modulo counter.  
     
     
       43. A method according to  claim 32 , in which the image data supplied during at least some of the addressing phases comprises or contains control data for controlling an aspect of pixel operation. 
     
     
       44. A method according to  claim 43 , in which the counter is a modulo counter having a modulo control input provided with a latching arrangement, 
       in which the aspect of pixel operation comprises the modulo of each modulo counter.  
     
     
       45. A method according to  claim 43 , in which the first and second counters are modulo counters having modulo control inputs provided with a latching arrangement, 
       in which the aspect of pixel operation comprises the modulo of each modulo counter.