Transistor device including buried source

Abstract

A transistor device includes a gate region disposed adjacent to a semiconductor substrate such that a low impedance channel is formed between a source region and drain region of a transistor device when a voltage is applied to its gate. The drain region of the device can be disposed aside the gate region on a common surface of the semiconductor substrate. The source region of the device also can be disposed adjacent to the substrate but on a side of the semiconductor substrate opposing the drain and/or gate regions. Based on this topology, a transistor device can be fabricated with a buried source to enhance its operating characteristics such as switching speed.

What is claimed is:  
     
       1. A transistor device, comprising: 
       a longitudinally extending non-doped substrate;  
       a source region extending within and along a longitundinal distance that is substantially shorter than a longitudinal extent of the substrate;  
       a channel layer doped less than the source region formed over the source region and the substrate, such that the source region does not extend into the channel layer; and  
       a gate region and a drain region commonly disposed on a main surface of said channel layer and not extending into the channel layer; said drain region being separated from said gate region; wherein said gate region is disposed vertically adjacent and across said channel layer from said source region.  
     
     
       2. The transistor device as in  claim 1 , wherein at least a portion of the source region is disposed vertically opposite the gate region and the channel is disposed between the gate and source regions. 
     
     
       3. The transistor device as in  claim 2 , wherein the gate region is in contact with the channel layer and covers a larger surface area than the source region. 
     
     
       4. The transistor device as in  claim 1 , wherein an electrode is electrically attached to the source region via an insulated conductor extending through the channel layer. 
     
     
       5. The transistor device as in  claim 1 , wherein the channel layer is formed of Gallium Arsenide. 
     
     
       6. The transistor device as in  claim 1 , wherein a voltage applied to the gate region generates a depletion region deep enough in the channel layer such that an impedance channel is formed between the drain and source regions. 
     
     
       7. The transistor device as in  claim 1 , wherein the transistor device is fabricated at least in part based on MESFET technology.