Versatile high voltage outputs using low voltage transistors

Abstract

A output driver architecture ( 100 ) is proposed that uses thin gate-oxide core and thin gate-oxide Drain-extended transistors that can directly interface with voltage supplies up to six times the normal rating of the transistor. A bias generator ( 101 ), level shifter ( 103 ) and output stage ( 105 ) are adapted to buffer an input signal with a voltage swing of less than the normal operating voltage of the transistors to an output signal with a voltage swing of up to approximately six times the normal operating voltage of the transistors. The bias generator is interfaced directly with a high voltage power supply and generates a bias voltage with a magnitude of less than the dielectric breakdown of the transistors internal to the level shifter and output stage. Further, the bias generator is adapted to sense the magnitude of the high voltage supply, and to automatically and continuously self-adjust the bias voltage in response to changes sensed in the magnitude of the high voltage supply such that the bias generator can be used for a continuous range of high voltage supplies up to 6 times the normal operating voltage of the transistors.

What is claimed is:  
     
       1. An output buffer apparatus, comprising: 
       an input for receiving input signaling having an input voltage swing between a reference voltage and an input voltage;  
       an output for providing output signaling having an output voltage swing between said reference voltage and an output voltage that is greater than said input voltage;  
       a level shifter coupled to said input for receiving said input voltage signaling, said level shifter including an input for receiving an intermediate voltage having a predetermined relationship relative to said output voltage, said level shifter responsive to said intermediate voltage for translating said input signaling into intermediate signaling having an intermediate voltage swing between said intermediate voltage and said output voltage;  
       an intermediate voltage generator having an input for receiving said output voltage, said intermediate voltage generator coupled to said level shifter and responsive to said output voltage for providing said intermediate voltage to said level shifter, said intermediate voltage generator responsive to a change in said output voltage for automatically adjusting said intermediate voltage to maintain said predetermined relationship thereof relative to said output voltage; and  
       an output stage coupled between said level shifter and said output for translating said intermediate signaling into said output signaling.  
     
     
       2. The apparatus of  claim 1 , wherein said predetermined relationship is that said intermediate voltage is less than said output voltage by a predetermined amount. 
     
     
       3. The apparatus of  claim 1 , wherein said intermediate voltage generator includes a drain extended transistor coupled between said output voltage and said reference voltage. 
     
     
       4. The apparatus of  claim 3 , wherein said intermediate voltage generator includes a compare circuit having a first input coupled to a source of said drain extended transistor and a second input for receiving a further reference voltage, said compare circuit having an output coupled to a gate of said drain extended transistor. 
     
     
       5. The apparatus of  claim 4 , wherein said intermediate voltage generator includes a first resistor connected between said reference voltage and a source of said drain extended transistor, and a second resistor connected between said output voltage and the drain of said drain extended transistor, and wherein the drain of said drain extended transistor provides said intermediate voltage. 
     
     
       6. The apparatus of  claim 5 , wherein said compare circuit includes an operational amplifier. 
     
     
       7. The apparatus of  claim 4 , wherein said compare circuit includes an operational amplifier. 
     
     
       8. The apparatus of  claim 3 , wherein said intermediate voltage generator includes a first resistor connected between said reference voltage and a source of said drain extended transistor, and a second resistor connected between said output voltage and the drain of said drain extended transistor, and wherein the drain of said drain extended transistor provides said intermediate voltage. 
     
     
       9. The apparatus of  claim 3 , wherein said drain extended transistor is an NMOS transistor. 
     
     
       10. An output buffer apparatus, comprising: 
       an input for receiving input signaling having an input voltage swing between a reference voltage and an input voltage;  
       an output for providing output signaling having an output voltage swing between said reference voltage and an output voltage that is greater than said input voltage;  
       a level shifter coupled to said input for receiving said input voltage signaling, said level shifter including an input for receiving an intermediate voltage having a predetermined relationship relative to said output voltage, said level shifter responsive to said intermediate voltage for translating said input signaling into intermediate signaling having an intermediate voltage swing between said intermediate voltage and said output voltage, said level shifter including a plurality of transistors connected in series between said reference voltage and said output voltage, wherein one of said plurality of transistors is a drain extended transistor;  
       an intermediate voltage generator having an input for receiving said output voltage, said intermediate voltage generator coupled to said level shifter and responsive to said output voltage for providing said intermediate voltage to said level shifter; and  
       an output stage coupled between said level shifter and said output for translating said intermediate signaling into said output signaling.  
     
     
       11. The apparatus of  claim 10 , wherein said level shifter includes a further plurality of transistors connected in series between said reference voltage and said output voltage, and connected in parallel with said first-mentioned plurality of transistors, and wherein one of said further plurality of transistors is a drain extended transistor. 
     
     
       12. The apparatus of  claim 11 , wherein said drain extended transistor of said first-mentioned plurality is cascoded with a transistor of said further plurality other than said drain extended transistor of said further plurality, and wherein said drain extended transistor of said further plurality is cascoded with a transistor of said first-mentioned plurality other than said drain extend transistor of said first-mentioned plurality. 
     
     
       13. The apparatus of  claim 12 , wherein said transistor of said first-mentioned plurality that is cascoded with said drain extended transistor of said further plurality is connected to said output voltage, and wherein said transistor of said further plurality that is cascoded with said drain extended transistor of said first-mentioned plurality is connected to said output voltage. 
     
     
       14. The apparatus of  claim 12 , wherein said drain extended transistors are PMOS transistors, and wherein each of said pluralities of transistors includes a drain extended NMOS transistor that is drain-connected to said drain extended PMOS transistor of said plurality. 
     
     
       15. An output buffer apparatus, comprising: 
       an input for receiving input signaling having an input voltage swing between a reference voltage and an input voltage;  
       an output for providing output signaling having an output voltage swing between said reference voltage and an output voltage that is greater than said input voltage;  
       a level shifter coupled to said input for receiving said input voltage signaling, said level shifter including an input for receiving an intermediate voltage having a predetermined relationship relative to said output voltage, said level shifter responsive to said intermediate voltage for translating said input signaling into intermediate signaling having an intermediate voltage swing between said intermediate voltage and said output voltage;  
       an intermediate voltage generator having an input for receiving said output voltage, said intermediate voltage generator coupled to said level shifter and responsive to said output voltage for providing said intermediate voltage to said level shifter; and  
       an output stage coupled between said level shifter and said output for translating said intermediate signaling into said output signaling, said output stage including first and second transistors connected in series between said output and one of said reference voltage and said output voltage, wherein one of said transistors is a drain extended transistor.  
     
     
       16. The apparatus of  claim 15 , wherein said output stage includes third and fourth transistors connected in series between said output and the other of said reference voltage and said output voltage, and wherein one of said third and fourth transistors is a drain extended transistor. 
     
     
       17. The apparatus of  claim 16 , wherein one of said drain extended transistors is an NMOS transistor and the other of said drain extended transistors is a PMOS transistor that is drain-connected to said NMOS transistor, and wherein said drains of said drain extended transistors are connected to said output. 
     
     
       18. An output buffering method, comprising: 
       receiving input signaling having an input voltage swing between a reference voltage and an input voltage;  
       in response to said input signaling, providing output signaling having an output voltage swing between said reference voltage and an output voltage that is greater than said input voltage;  
       producing in response to said output voltage an intermediate voltage having a predetermined relationship relative to said output voltage, including automatically adjusting said intermediate voltage in response to a change in said output voltage to maintain said predetermined relationship of said intermediate voltage relative to said output voltage; and  
       said providing step including translating said input signaling into intermediate signaling having an intermediate voltage swing between said intermediate voltage and said output voltage, and translating said intermediate signaling into said output signaling.  
     
     
       19. The method of  claim 18 , wherein said predetermined relationship is that said intermediate voltage is less than said output voltage by a predetermined amount. 
     
     
       20. The method of  claim 18 , wherein said output voltage is more than twice as large as said input voltage. 
     
     
       21. An analog controlled high-voltage interfaced bias circuit which comprises: 
       an operational amplifier having a reference input, a second input and an output; a power supply;  
       a first resistor coupled having a pair of opposing terminals, one of said opposing terminals coupled to a source of reference voltage;  
       a second resistor having a pair of opposing terminals, one of said opposing terminals coupled to said power supply;  
       a drain extended transistor having a gate coupled to said output of said operational amplifier, an extended drain coupled to the other of said opposing terminals of said second resistor and a source coupled to said second input and the other of said opposing terminals of said first resistor; and  
       a capacitor coupled across said second resistor.  
     
     
       22. The circuit of  claim 21  wherein the resistances of said first and second resistors have a predetermined ratio based upon the voltage at said reference input of said operational amplifier. 
     
     
       23. A controlled high-voltage interfaced bias circuit, which comprises: 
       a power supply;  
       a reference voltage source;  
       a plurality of cascaded MOS diodes, one end of said cascaded diodes coupled to said reference voltage source;  
       a capacitor coupled between said reference voltage source and the other end of said cascaded diodes; and  
       a source follower coupled between said power supply and said other end of said cascaded diodes.  
     
     
       24. The circuit of  claim 23  wherein said source follower comprises a resistor, one end of said resistor coupled to said power supply, a first drain extended MOS transistor with the extended drain coupled between said other end of said resistor and the other end of said cascaded diodes, the gate of said first drain extended MOS transistor coupled to said one end of said resistor, and a second drain extended MOS transistor having a gate coupled to said extended drain of said first drain extended MOS transistor, an extended drain coupled to said power supply and a source coupled to said other end of said cascaded MOS diodes. 
     
     
       25. The circuit of  claim 24  wherein said cascaded diodes are NMOS transistors. 
     
     
       26. A controlled high-voltage interfaced bias circuit, which comprises: 
       a power supply;  
       a reference voltage source;  
       a plurality of cascaded MOS diodes, one end of said cascaded diodes coupled to said power supply;  
       a capacitor coupled between said power supply and the other end of said cascaded diodes; and  
       a source follower coupled between said reference voltage source and said other end of said cascaded diodes.  
     
     
       27. The circuit of  claim 26  wherein said source follower comprises a resistor, one end of said resistor coupled to said power supply, a first drain extended MOS transistor with the extended drain coupled between said other end of said resistor and the other end of said cascaded diodes, the gate of said first drain extended MOS transistor coupled to said one end of said resistor, and a second drain extended MOS transistor having a gate coupled to said extended drain of said first drain extended MOS transistor, an extended drain coupled to said power supply and a source coupled to said other end of said cascaded MOS diodes. 
     
     
       28. The circuit of  claim 27  wherein said cascaded diodes are PMOS transistors.