Frequency divider with reduced jitter and apparatus based thereon

Abstract

A circuit generates an output signal whose frequency is lower than the frequency of an input signal. In an example embodiment, there is a chain of frequency dividing cells. Each of the frequency dividing cells has a pre-defined division ratio and a clock input for receiving an input clock, a divided clock output for providing an output clock to a subsequent frequency dividing cell, a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell, and a mode control output for providing a mode control output signal to a preceding frequency dividing cell. Further included are a latch for altering the division ratio of each of the frequency dividing cells and D-Flip-Flop circuitry having two latches. A first signal clocks the first latch and a second signal clocks the second latch, whereby the frequency of the first signal is lower than the frequency of the second signal.

1. Apparatus for generating an output signal whose frequency is lower than the frequency of an input signal, the apparatus comprising:
 a chain of frequency dividing cells, wherein each of the frequency dividing cells has a pre-defined division ratio and comprises 
 a clock input for receiving an input clock;  
 a divided clock output for providing an output clock to a subsequent frequency dividing cell;  
 a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell; and  
 a mode control output for providing a mode control output signal to a preceding frequency dividing cell;  
 a latch for altering the division ratio of each the frequency dividing cells,  
 a D-Flip-Flop circuitry with two latches, the first latch being clocked by a first signal output from the subsequent frequency dividing cell and the second latch being clocked by a second signal input to the preceding frequency dividing cell,  
 whereby the frequency of the first signal is lower than the frequency of the second signal.  
 
 
     
     
       2. The apparatus of  claim 1 , wherein the second signal is a signal tapped from the input signal. 
     
     
       3. The apparatus of  claim 1 , wherein the first signal is a signal tapped at one of the divided clock outputs within the chain of frequency dividing cells. 
     
     
       4. The apparatus of  claim 1 , wherein the D-Flip-Flop circuitry has an input being connected to one of the mode control inputs within the chain of frequency dividing cells. 
     
     
       5. The apparatus of  claim 1 , comprising an output circuitry for processing the output signal provided at an output of the second latch in order to provide another output signal. 
     
     
       6. The apparatus of  claim 1 , wherein
 the input signal to be divided is applicable to the clock input of one frequency dividing cell ( 71 ;  81 ) of the chain of frequency dividing cells,  
 the divided clock output of the one frequency dividing cell of the chain of frequency dividing cells is connected to the clock input of the subsequent frequency dividing cell of the chain of frequency dividing cells,  
 the mode control input of the one frequency dividing cell of the chain of frequency dividing cells is connected to the mode control output of the subsequent frequency dividing cell of the chain of frequency dividing cells.  
 
     
     
       7. The apparatus of  claim 1 , wherein the frequency dividing cells are divide-by-⅔ cells, wherein the division ratio (N/M) is switchable between 2 and 3. 
     
     
       8. The apparatus of  claim 1 , comprising latches being realized in current-mode logic (CML), wherein the latches include at least one of the following:
 the latch for altering the division ratio of each the frequency dividing cells,  
 the first latch and second latch of the D-Flip-Flop circuitry.  
 
     
     
       9. The apparatus of  claim 1 , wherein each frequency dividing cell of the chain of frequency dividing cells comprises a programming input for application of a binary code word allowing together with the mode control input signals the division ratio (N/M) of the frequency dividing cells to be switched. 
     
     
       10. The apparatus of  claim 1 , wherein the chain of frequency dividing cells is realized according to a zipper divider architecture. 
     
     
       11. A transmitter or receiver system in a CMOS system, comprising an apparatus according to  claim 1 .