ESD/EOS protection structure for integrated circuit devices

Abstract

Apparatus and methods forming electrostatic discharge and electrical overstress protection devices for integrated circuits wherein such devices include shared electrical contact between source regions and between drain regions for more efficient dissipation of an electrostatic discharge. The devices further include contact plugs and contact lands which render the fabrication of the devices less sensitive to alignment constraint in the formation of contacts for the device.

1. A transistor for the dissipation of electrostatic discharges, comprising:
 an intermediate structure comprising a substrate having at least one thick field oxide area, and at least one active area including at least one implanted drain region, and at least one implanted source region, the intermediate structure further including at least one transistor gate member spanned between the at least one implanted drain region and the at least one implanted source region on the at least one active area;  
 a first barrier layer planarized down to the at least one transistor gate member and substantially covering the at least one thick field oxide area and the at least one active area, and adjacent the at least one transistor gate member;  
 at least one drain contact plug extending through the first barrier layer, wherein the at least one drain contact plug is in electrical communication with the at least one implanted drain region on the substrate;  
 at least one source contact plug extending through the first barrier layer, wherein the at least one source contact plug is in electrical communication with the at least one implanted source region on the substrate;  
 an individual drain contact land disposed atop the at least one drain contact plug and a portion of the first barrier layer, the individual drain contact land wider than the at least one drain contact plug;  
 an individual source contact land disposed atop the at least one source contact plug and a portion of the first barrier layer, the individual source contact land wider than the at least one source contact plug;  
 a second barrier layer disposed over the first barrier layer, the individual drain contact land, and the individual source contact land;  
 at least one upper source contact extending through the second barrier layer, the at least one upper source contact in electrical communication with the individual source contact land; and  
 at least one upper drain contact extending through the second barrier layer, the at least one upper drain contact in electrical communication with the individual drain contact land.  
 
   
   
     2. The transistor of  claim 1 , further comprising drain contact metallization in electrical communication with the at least one upper drain contact; and source contact metallization in electrical communication with the at least one upper source contact. 
   
   
     3. The transistor of  claim 1 , wherein the at least one source contact plug extends between at least two source regions. 
   
   
     4. The transistor of  claim 1 , wherein the at least one drain contact plug extends between at least two drain regions. 
   
   
     5. The transistor of  claim 1 , wherein the at least one upper source contact extends between at least two individual source contact lands. 
   
   
     6. The transistor of claims  1 , wherein the at least one upper drain contact extends between at least two individual drain contact lands. 
   
   
     7. A semiconductor device including at least one transistor for the dissipation of electrostatic discharges, comprising:
 an intermediate structure comprising a semiconductor substrate having at least one thick field oxide area, and at least one active area including at least one implanted drain region, and at least one implanted source region, the intermediate structure further including at least one transistor gate member spanned between the at least one implanted drain region and the at least one implanted source region on the at least one active area;  
 a first barrier layer planarized down to the at least one transistor gate member and substantially covering the at least one thick field oxide area, the at least one active area, and adjacent the at least one transistor gate member;  
 at least one drain contact plug extending through the first barrier layer, wherein the at least one drain contact plug is in electrical communication with the at least one implanted drain region on the semiconductor substrate;  
 at least one source contact plug extending through the first barrier layer, wherein the at least one source contact plug is in electrical communication with the at least one implanted source region on the semiconductor substrate;  
 an individual drain contact land disposed atop the at least one drain contact plug and a portion of the first barrier layer, the individual drain contact land wider than the at least one drain contact plug;  
 an individual source contact land disposed atop the at least one source contact plug and a portion of the first barrier layer, the individual source contact land wider than the at least one source contact plug;  
 a second barrier layer disposed over the first barrier layer;  
 at least one upper source contact extending through the second barrier layer, the at least one upper source contact in electrical communication with the individual source contact land; and  
 at least one upper drain contact extending through the second barrier layer, the at least one upper drain contact in electrical communication with the individual drain contact land.  
 
   
   
     8. The semiconductor device of  claim 7 , further comprising drain contact metallization in electrical communication with the at least one upper drain contact; and source contact metallization in electrical communication with the at least one upper source contact. 
   
   
     9. The semiconductor device of  claim 7 , wherein the at least one source contact plug extends between at least two source regions. 
   
   
     10. The semiconductor device of  claim 7 , wherein the at least one drain contact plug extends between at least two drain regions. 
   
   
     11. The semiconductor device of  claim 7 , wherein the at least one upper source contact extends between at least two individual source contact lands. 
   
   
     12. The semiconductor device of  claim 7 , wherein the at least one upper drain contact extends between at least two individual drain contact lands. 
   
   
     13. A contact for a semiconductor device, comprising:
 a single contact plug extending through a first barrier layer and a second barrier layer, the second barrier layer disposed over the first barrier layer and planarized down to a transistor gate member, the single contact plug being in electrical communication with an active region on a semiconductor substrate;  
 an individual contact land disposed atop the single contact plug and a portion of the second barrier layer, wherein the individual contact land is wider than the single contact plug; and  
 an upper contact extending through a third barrier layer, the third barrier layer disposed over the second barrier layer, to form an electrical contact with the individual contact land.  
 
   
   
     14. A transistor for the dissipation of electrostatic discharges, comprising:
 an intermediate structure comprising a substrate having at least one thick field oxide area, and at least one active area including at least one implanted drain region, and at least one implanted source region, the intermediate structure further including at least one transistor gate member spanned between the at least one implanted drain region and the at least one implanted source region on the at least one active area;  
 a first barrier layer substantially covering the at least one thick field oxide area and the at least one active area, and adjacent the at least one transistor gate member;  
 a second barrier layer disposed over the first barrier layer and planarized down to the at least one transistor gate member;  
 at least one drain contact plug extending through each of the first and second barrier layers, wherein the at least one drain contact plug is in electrical communication with the at least one implanted drain region on the substrate;  
 at least one source contact plug extending through each of the first and second barrier layers, wherein the at least one source contact plug is in electrical communication with the at least one implanted source region on the substrate;  
 an individual drain contact land disposed atop the at least one drain contact plug and a portion of the second barrier layer, the individual drain contact land wider than the at least one drain contact plug;  
 an individual source contact land disposed atop the at least one source contact plug and a portion of the second barrier layer, the individual source contact land wider than the at least one source contact plug;  
 a third barrier layer disposed over the second barrier layer, the individual drain contact land, and the individual source contact land;  
 at least one upper source contact extending through the third barrier layer, the at least one upper source contact in electrical communication with the individual source contact land; and  
 at least one upper drain contact extending through the third barrier layer, the at least one upper drain contact in electrical communication with the individual drain contact land.  
 
   
   
     15. A semiconductor device including at least one contact, comprising:
 a single contact plug extending through each of a first barrier layer and a second barrier layer, the second barrier disposed over the first barrier layer and planarized down to a transistor gate member, the single contact plug being in electrical communication with an active region on a semiconductor substrate;  
 an individual contact land disposed atop the single contact plug and a portion of the second barrier layer, the individual contact land being wider than the single contact plug; and  
 an upper contact extending through a third barrier layer, the third barrier layer disposed over the second barrier layer, to form an electrical contact with the individual contact land.  
 
   
   
     16. A semiconductor device including at least one transistor for the dissipation of electrostatic discharges, comprising:
 an intermediate structure comprising a semiconductor substrate having at least one thick field oxide area, and at least one active area including at least one implanted drain region, and at least one implanted source region, the intermediate structure further including at least one transistor gate member spanned between the at least one implanted drain region and the at least one implanted source region on the at least one active area;  
 a first barrier layer substantially covering the at least one thick field oxide area and the at least one active area, and adjacent the at least one transistor gate member;  
 second barrier layer disposed over the first barrier layer and planarized down to the at least one transistor gate member;  
 at least one drain contact plug extending through each of the first and second barrier layers, wherein the at least one drain contact plug is in electrical communication with the at least one implanted drain region on the semiconductor substrate;  
 at least one source contact plug extending through each of the first and second barrier layers, wherein the at least one source contact plug is in electrical communication with the at least one implanted source region on the semiconductor substrate;  
 an individual drain contact land disposed atop the at least one drain contact plug and a portion of the second barrier layer, the individual drain contact land being wider than the at least one drain contact plug;  
 an individual source contact land disposed atop the at least one source contact plug and a portion of the second barrier layer, the individual source contact land being wider than the at least one source contact plug;  
 a third layer disposed over the second barrier layer, the individual source contact land and the individual drain contact land;  
 at least one upper source contact extending through the third barrier layer, the at least one upper source contact being in electrical communication with the individual source contact land; and  
 at least one upper drain contact extending through the third barrier layer, the at least one upper source contact being in electrical communication with the individual drain contact land.