Operational amplifier with adjustable input offset

Abstract

An operational amplifier having an adjustable input offset is provided that can improve dynamic performance by allowing processing of the input signal in continuous-time. The amplifier circuit comprises an input source and an operational amplifier configured with an adjustable input offset circuit. The adjustable input offset circuit enables cancellation of the offset error from any input sources prior to being translated or gained up by the operational amplifier, thus improving the dynamic range of the operational amplifier. The adjustable input offset circuit can be configured within a signal path of an auto-zero loop of the operational amplifier, or with a continuous-time implementation.

1. An operational amplifier configured to provide offset correction, said operational amplifier comprising:
 an amplifier having an offset voltage, said amplifier configured for receiving an input signal having an offset voltage and for providing an amplified output signal, said amplifier comprising an adjustable input offset voltage source configured for providing an adjustable offset; and  
 wherein said adjustable offset is configured to sum with said offset voltage of said amplifier to provide an offset correction voltage to cancel said offset voltage of said input signal to prevent said offset voltage of said input signal from being translated through said amplifier to said amplified output signal.  
 
   
   
     2. An operational amplifier configured to provide offset correction, said operational amplifier comprising:
 an amplifier having an offset voltage, said amplifier configured for receiving an input signal having an offset voltage and for providing an amplified output signal, said amplifier comprising an adjustable input offset circuit configured for providing an adjustable offset; and  
 wherein said adjustable offset is configured to sum with said offset voltage of said amplifier to provide an offset correction voltage to cancel said offset voltage of said input signal to prevent said offset voltage of said input signal from being translated through said amplifier to said amplified output signal,  
 wherein said amplifier is configured in a continuous-time implementation comprising:  
 a first stage G m1  configured in a direct signal path and having an output;  
 a second stage G m2  having input terminals coupled to said adjustable input offset circuit and an output terminal summed with said output of said first stage G m1 ; and  
 an output stage A 1  having an input terminal coupled to said summed output terminal of said second stage G m2  and said output of said first stage G m1 .  
 
   
   
     3. The operational amplifier according to  claim 2 , wherein said amplifier is configured in an auto-zero loop configuration. 
   
   
     4. The operational amplifier according to  claim 3 , wherein said amplifier comprises:
 a direct signal path comprising a first stage G m1  and having an output terminal, and an output stage A 1  having an input terminal coupled to said output terminal of said first stage G m1 ; and  
 an auto-zero loop comprising a second stage G m2  having input terminals coupled to said adjustable input offset circuit, a fourth stage G m4  having an output terminal summed with an output terminal of said second stage G m2 , and a third stage G m3  having an input terminal coupled to said output terminal of said fourth stage G m4  and an output terminal summed with said output terminal of said first stage G m1 .  
 
   
   
     5. The operational amplifier according to  claim 3 , wherein said amplifier comprises a first switch and a second switch, said first switch is configured to couple a first stage G m1  during a first phase, and said second switch is configured to couple said auto-zero loop to said adjustable input offset circuit during a second phase. 
   
   
     6. The operational amplifier according to  claim 3 , wherein said auto-zero loop configuration is configured for dual-phase operation. 
   
   
     7. The operational amplifier according to  claim 6 , wherein said auto-zero loop configuration comprises a first block comprising said adjustable offset circuit, a second block and a third block, each comprising a second stage G m2  and a fourth stage G m4 , and a fourth block comprising a first stage G m1 , a third stage G m3 , and an output stage A 1 . 
   
   
     8. The operational amplifier according to  claim 7 , wherein said auto-zero loop configuration comprises a single storage capacitor in each of said second and third blocks. 
   
   
     9. The operational amplifier according to  claim 2 , wherein said adjustable input offset circuit comprises a positive terminal coupled through a switch to a positive input terminal of a second stage G m2  of said amplifier, and a negative input terminal coupled directly to a negative input terminal of said second stage G m2 . 
   
   
     10. The operational amplifier according to  claim 1 , wherein said operational amplifier comprises an input source configured for providing said input signal to said amplifier. 
   
   
     11. An amplifier circuit for cancellation of offset error caused by an input source coupled to an operational amplifier, said amplifier circuit comprising:
 an amplifier configured for receiving an output signal from an input source, and for providing an amplified output signal, said amplifier having an offset error; and  
 an adjustable offset input voltage source coupled to said amplifier and configured to provide an adjustable offset, said amplifier circuit being configured to sum said adjustable offset with said offset error of said amplifier to provide an offset correction voltage, said offset correction voltage configured to cancel the offset error of an input source to prevent the offset error of the input source from being translated through said amplifier to said amplified output signal.  
 
   
   
     12. An amplifier circuit for cancellation of offset error caused by an input source coupled to an operational amplifier, said amplifier circuit comprising:
 an amplifier configured for receiving an output signal from an input source, and for providing an amplified output signal, said amplifier having an offset error; and  
 an adjustable offset input circuit coupled to said amplifier and configured to provide an adjustable offset, said amplifier circuit being configured to sum said adjustable offset with said offset error of said amplifier to provide an offset correction voltage, said offset correction voltage configured to cancel the offset error of an input source to prevent the offset error of the input source from being translated through said amplifier to said amplified output signal,  
 wherein said amplifier is configured in a continuous-time implementation comprising:  
 a first stage G m1  configured in a direct signal path and having an output;  
 a second stage G m2  having input terminals coupled to said adjustable input offset circuit and an output terminal summed with said output of said first stage G m1 ; and  
 an output stage A 1  having an input terminal coupled to said summed output terminal of said second stage G m2  and said output of said first stage G m1 .  
 
   
   
     13. The amplifier circuit according to  claim 11 , wherein said amplifier is configured in an auto-zero loop configuration. 
   
   
     14. The amplifier circuit according to  claim 13 , wherein said auto-zero loop configuration is configured for dual-phase operation. 
   
   
     15. An amplifier circuit for cancellation of offset error caused by an input source coupled to an operational amplifier, said amplifier circuit comprising:
 an amplifier configured for receiving an output signal from an input source, and for providing an amplified output signal, said amplifier having an offset error; and  
 an adjustable offset input circuit coupled to said amplifier and configured to provide an adjustable offset, said amplifier circuit being configured to sum said adjustable offset with said offset error of said amplifier to provide an offset correction voltage, said offset correction voltage configured to cancel the offset error of an input source to prevent the offset error of the input source from being translated through said amplifier to said amplified output signal,  
 wherein said amplifier comprises:  
 a direct signal path comprising a first stage G m1  and having an output terminal, and an output stage A 1  having an input terminal coupled to said output terminal of said first stage G m1 ; and  
 an auto-zero loop comprising a second stage G m2  having input terminals coupled to said adjustable input offset circuit, a fourth stage G m4  having an output terminal summed with an output terminal of said second stage G m2 , and a third stage G m3  having an input terminal coupled to said output terminal of said fourth stage G m4  and an output terminal summed with said output terminal of said first stage G m1 .  
 
   
   
     16. An amplifier circuit for cancellation of offset error caused by an input source coupled to an operational amplifier, said amplifier circuit comprising:
 an amplifier configured for receiving an output signal from an input source, and for providing an amplified output signal, said amplifier having an offset error; and  
 an adjustable offset input circuit coupled to said amplifier and configured to provide an adjustable offset, said amplifier circuit being configured to sum said adjustable offset with said offset error of said amplifier to provide an offset correction voltage, said offset correction voltage configured to cancel the offset error of an input source to prevent the offset error of the input source from being translated through said amplifier to said amplified output signal,  
 wherein said amplifier is configured in an auto-zero loop configuration, and  
 wherein said amplifier comprises a first switch and a second switch, said first switch is configured to couple a first stage G m1  to said auto-zero loop during a first phase, and said second switch is configured to couple said auto-zero loop to said adjustable input offset circuit during a second phase.  
 
   
   
     17. A method for providing an adjustable offset reference to an operational amplifier to cancel input offset error caused by an input source coupled to an input stage G m  of said operational amplifier, said method comprising the steps of:
 providing an adjustable offset voltage VOS REF  across input terminals of a second stage G m ;  
 generating an output error in said operational amplifier based on a magnitude of said adjustable offset voltage VOS REF ; and  
 summing said output error with the input output error caused by the input source such that said input offset error is reduced prior to translating said input offset error through said operational amplifier.  
 
   
   
     18. The method according to  claim 17 , wherein the step of generating said output error is conducted within an auto-zero loop configuration. 
   
   
     19. The method according to  claim 18 , wherein said step of providing said adjustable offset voltage VOS REF  comprises coupling through a first switch to an auto-zero loop during a first phase, and coupling through a second switch said auto-zero loop to said adjustable offset voltage VOS REF  during a second phase. 
   
   
     20. The method according to  claim 17 , wherein the step of generating said output error is conducted within an auto-zero loop configured for dual-phase operation. 
   
   
     21. The method according to  claim 17 , wherein the step of generating said output error is conducted in a continuous-time implementation. 
   
   
     22. An amplifier circuit for cancellation of offset error caused by an input source coupled to an operational amplifier, said amplifier circuit comprising:
 an amplifier configured for receiving an output signal from an input source and for providing an amplified output signal, said amplifier having an offset error, said amplifier comprising a direct signal path and an auto-zero loop; and  
 an adjustable offset input voltage source coupled to said amplifier and configured to provide an adjustable offset; and  
 wherein said auto-zero loop is configured to sum said adjustable offset with said offset error of said amplifier to provide an offset correction voltage, said offset correction voltage configured to cancel the offset error of an input source to prevent the offset error of the input source from being translated through said amplifier to said amplified output signal.  
 
   
   
     23. An amplifier circuit for cancellation of offset error caused by an input source coupled to an operational amplifier, said amplifier circuit comprising:
 an amplifier configured for receiving an output signal from an input source and for providing an amplified output signal, said amplifier having an offset error, said amplifier comprising a direct signal path and an auto-zero loop; and  
 an adjustable offset input circuit coupled to said amplifier and configured to provide an adjustable offset; and  
 wherein said auto-zero loop is configured to sum said adjustable offset with said offset error of said amplifier to provide an offset correction voltage, said offset correction voltage configured to cancel the offset error of an input source to prevent the offset error of the input source from being translated through said amplifier to said amplified output signal, and  
 wherein said direct signal path comprises a first stage G m1  and having an output terminal, and an output stage A 1  having an input terminal coupled to said output terminal of said first stage G m1 , and said auto-zero loop comprises a second stage G m2  having input terminals coupled to said adjustable input offset circuit, a fourth stage G m4  having an output terminal summed with an output terminal of said second stage G m2 , and a third stage G m3  having an input terminal coupled to said output terminal of said fourth stage G m4  and an output terminal summed with said output terminal of said first stage G m1 .  
 
   
   
     24. An amplifier circuit for cancellation of offset error caused by an input source coupled to an operational amplifier, said amplifier circuit comprising:
 an amplifier configured for receiving an output signal from an input source and for providing an amplified output signal, said amplifier having an offset error, said amplifier comprising a direct signal path and an auto-zero loop; and  
 an adjustable offset input circuit coupled to said amplifier and configured to provide an adjustable offset; and  
 wherein said auto-zero loop is configured to sum said adjustable offset with said offset error of said amplifier to provide an offset correction voltage, said offset correction voltage configured to cancel the offset error of an input source to prevent the offset error of the input source from being translated through said amplifier to said amplified output signal, and  
 wherein said amplifier comprises a first switch and a second switch, said first switch is configured to couple a first stage G m1  to said auto-zero loop during a first phase, and said second switch is configured to couple said auto-zero loop to said adjustable input offset circuit during a second phase.