Frequency-stabilized transceiver configuration

Abstract

A transceiver configuration has an integrated circuit (IC) with an A/D and/or D/A converter, a VCO with a reference oscillator, which provides a sampling clock for the A/D and/or D/A converter, and a digital data processing circuit. The IC is connected to a radio-frequency section, the frequency converter stage of which is operated with a beat frequency derived from the controllable oscillator frequency f oz . A capacitive resonant element of the reference oscillator is disposed outside of the IC.

1. A transceiver configuration for a communication terminal, comprising:
 an A/D converter outputting a first digital data signal;  
 a D/A converter;  
 a controllable oscillator circuit connected to said A/D converter and to said D/A converter, said controllable oscillator circuit having a reference oscillator with an oscillating crystal as a resonator and outputs a sampling clock received by said A/D converter and said D/A converter;  
 a digital data processing circuit connected to said A/D converter and to said D/A converter and receives the first digital data signal output by said A/D converter and processes it further and outputs a second digital data signal to said D/A converter;  
 said A/D converter, said D/A converter, said data processing circuit and said controllable oscillator circuit, apart from said oscillating crystal of said reference oscillator, being constructed as a monolithically integrated circuit so that of said controllable oscillator circuit, only said oscillating crystal is implemented as an external component; and  
 a frequency section being at least one of a radio-frequency section and an intermediate-frequency section connected to said A/D converter, to said D/A converter and to said controllable oscillator circuit, said frequency section having a frequency converter stage operating with a beat frequency derived from said controllable oscillator circuit.  
 
     
     
       2. The transceiver configuration according to  claim 1 , wherein said digital data processing circuit has a digital filter and a digital modulator. 
     
     
       3. The transceiver configuration according to  claim 1 , wherein said digital data processing circuit has a channel estimator. 
     
     
       4. The transceiver configuration according to  claim 3 , including a data detector connected to said channel estimator.