CMOS image sensor with substrate noise barrier

Abstract

An image sensor element includes a vertical overflow drain structure to eliminate substrate charge diffusion causing CMOS image sensor noise. An extra chemical mechanical polish step used to shorten the micro-lens to silicon surface distance in order to reduce optical cross talking. One embodiment uses N type substrate material with P− epitaxial layer to form a vertical overflow drain. Deep P well implantation is introduced to the standard CMOS process to prevent latch-up between an N well to an N type substrate. A photo diode is realized by stacked N well/Deep N well and stacked P well/Deep P well to improve performance.

1. A method of forming a CMOS image sensor, the method comprising:
 forming a substrate with a first layer being a first conductive type of a semiconductor material and a second layer being a second conductive type, the second layer being on top of the first layer and fully covering the first layer so as to form a junction therebetween that prevents substrate noise diffused into photo elements when a first voltage is applied to the first layer and a second voltage is applied to the second layer, wherein the junction is reversely biased, and  
 wherein the CMOS image sensor is integrated with accessory CMOS circuits to facilitate the CMOS Image sensor to operate as desired.  
 
   
   
     2. The method as in  claim 1 , wherein the junction is so formed to be a substrate noise barrier in the CMOS image sensor. 
   
   
     3. The method as in  claim 1 , further comprising:
 forming a deep well of the second conductive type in the second layer to prevent latch-up between the accessory CMOS circuits and the first layer.  
 
   
   
     4. The method as in  claim 1 , further comprising:
 forming a photodiode element, the photodiode element having a first well region of the first conductive type formed in the second layer of the second conductive type; and  
 causing a second well region of the second conductive type to be formed in the second layer of the second conductive type with higher doping density than that of the second layer of the second conductive type.  
 
   
   
     5. The method as in  claim 4 , wherein the second well surrounds the first well region to form a lateral PN Junction. 
   
   
     6. The method as in  claim 5 , wherein the first well region and the second layer of the second conductive type forms a vertical PN Junction. 
   
   
     7. The method as in  claim 6 , wherein both the lateral PN junction and vertical junction are reversely biased. 
   
   
     8. The method as in  claim 1 , wherein a distance between a micro-lens and a photo element in the CMOS image sensor is reduced by adding an extra process of chemical mechanical polishing (CMP) to eliminate a conventional planarization layer such that sensitivity of the photo element is increased. 
   
   
     9. The method as in  claim 1 , further comprising:
 forming a deep well of the second conductive type in the second layer to prevent latch-up between the accessory CMOS circuits and the first layer, and  
 wherein the deep well is formed at a center depth in a range of 0.5 um to 2 um for a thickness in a range of 0.5 um to 2 um with the second conductive type doping outside the photo element to prevent the latch-up to happen.  
 
   
   
     10. The method as in  claim 1 , further comprising:
 growing a top oxide layer on top of the second layer; and  
 carrying out a process of chemical mechanical polishing (CMP).  
 
   
   
     11. The method as in  claim 1 ,
 wherein the first layer is of N type, and the second layer is of P type, and  
 wherein the first voltage is higher than the second voltage.  
 
   
   
     12. The method as in  claim 1 ,
 wherein the first layer is of P type, and the second layer is of N type; and  
 wherein the first voltage is lower than the second voltage.  
 
   
   
     13. A CMOS image sensor comprising:
 a substrate including a first layer being a first type of a semiconductor material end a second layer being a second type of a semiconductor material disposed on top of first layer and fully covering the first layer to form a junction that prevents substrate noise diffused to photo elements when a first voltage is applied to the first layer and a second voltage is applied to the second layer, wherein the junction is reversely biased, and  
 wherein the CMOS image sensor is integrated with accessory CMOS circuits to facilitate the CMOS Image sensor to operate.  
 
   
   
     14. The CMOS image sensor of  claim 13 , wherein the junction is so formed to be a substrate noise barrier that prevents substrate noise diffused into other photo elements in the CMOS image sensor. 
   
   
     15. The CMOS image sensor of  claim 14 , wherein a deep well of the second conductive type is formed in the second layer to prevent latch-up between the accessory CMOS circuits and the first layer. 
   
   
     16. The CMOS image sensor of  claim 13  the first layer is of N type, and the second layer is of P type, and wherein the first voltage is higher than the second voltage. 
   
   
     17. The CMOS image sensor of  claim 16 , wherein a deep well of P type is formed in the second layer to prevent latch-up between wells to form a photo element and the first layer. 
   
   
     18. The CMOS image sensor of  claim 13 , wherein the first layer is of P type, and the second layer is of N type, and wherein the first voltage is lower than the second voltage. 
   
   
     19. The CMOS image sensor of  claim 18 , wherein a deep well of N type is formed in the second layer to prevent latch-up between wells to form a photo element and the first layer. 
   
   
     20. The CMOS image sensor of  claim 13 , wherein a distance between a micro-lens and one of the photo diodes is reduced by adding an extra process of chemical mechanical polishing (CMP) to eliminate a conventional planarization layer such as a sensitivity of the one of the photo diodes is increased.