Reducing variation in randomized nanoscale circuit connections

Abstract

A method and apparatus of reducing variations in nanoscale circuit connections. One exemplary embodiment includes: placing a first connector between a first addressing wire and a first nanowire in a partial circuit; and applying bias to the partial circuit so that a second connector is placed between a second addressing wire and a second nanowire. This method of bias connections is repeated for each wire in the full circuit. Thus, bias is used to influence the positioning of connectors on additional wires (if any) in the full circuit.

1. A method of reducing variations in nanoscale circuit connections, the method comprising:
 placing a first connector between a first addressing wire and a first nanowire in a partial circuit; and  
 applying bias to the partial circuit so that a second connector is placed between a second addressing wire and a second nanowire, wherein applying the bias permits a reduction in variance in a number of connectors in each nanowire.  
 
     
     
       2. The method of  claim 1 , wherein applying the bias comprises:
 introducing a voltage on at least the first addressing wire.  
 
     
     
       3. The method of  claim 1 , wherein applying the bias comprises:
 placing a charge on the first nanowire and second nanowire.  
 
     
     
       4. The method of  claim 1 , further comprising:
 placing a first connector between a first addressing wire and a first nanowire in another partial circuit that will form a full circuit; and  
 applying bias to the another partial circuit so that a second connector is placed between a second addressing wire and a second nanowire in the another partial circuit so as to reduce variance in the number of connectors.  
 
     
     
       5. The method of  claim 1 , wherein a reduction in variance in the number of connectors in each nanowire permits a reduction in a number of addressing wires. 
     
     
       6. The method of  claim 4 , wherein a reduction in variance in the number of connectors in each nanowire permits a reduction in a number of addressing wires. 
     
     
       7. A nanoscale circuit produced in accordance with the method of  claim 1 . 
     
     
       8. A nanoscale circuit produced in accordance with the method of  claim 4 . 
     
     
       9. An apparatus for reducing variations in nanoscale circuit connections, the apparatus comprising:
 means for placing a first connector between a first addressing wire and a first nanowire in a partial circuit; and  
 means for applying bias to the partial circuit so that a second connector is placed between a second addressing wire and a second nanowire, wherein the bias permits a reduction in variance in a number of connectors in each nanowire.  
 
     
     
       10. A nanoscale circuit, comprising:
 a first addressing wire;  
 a first nanowire;  
 a first connector placed between the first addressing wire and a first nanowire in a partial circuit in a random manner;  
 a second addressing wire;  
 a second nanowire; and  
 a second connector placed between the second addressing wire and a second nanowire by application of bias to the partial circuit.  
 
     
     
       11. The nanoscale circuit of  claim 10 , wherein application of the bias permits a reduction in variance in a number of connectors in each nanowire. 
     
     
       12. The nanoscale circuit of  claim 10 , wherein the bias is applied to the partial circuit by introduction of a voltage on at least the first addressing wire. 
     
     
       13. The nanoscale circuit of  claim 10 , wherein the bias is applied to the partial circuit by placement of a charge on the first nanowire and second nanowire. 
     
     
       14. The nanoscale circuit of  claim 10 , wherein:
 another connector is placed between a first addressing wire and a first nanowire in another partial circuit that will form a full circuit; and  
 applying bias to the another partial circuit so that an additional connector is placed between a second addressing wire and a second nanowire in the another partial circuit.  
 
     
     
       15. The nanoscale circuit of  claim 10 , further comprising:
 a first addressing wire in another partial circuit;  
 a first nanowire in the another partial circuit;  
 a first connector placed between the first addressing wire and a first nanowire in the another partial circuit;  
 a second addressing wire in the another partial circuit;  
 a second nanowire in the another partial circuit;  
 a second connector placed between the second addressing wire and a second nanowire in the another partial circuit by application of bias to the partial circuit.  
 
     
     
       16. A method of reducing variations in nanoscale circuit connections, comprising:
 placing a first connector between a first addressing wire and a first nanowire in a partial circuit; and  
 applying bias to the partial circuit to influence a positioning of a second connector on a second nanowire.  
 
     
     
       17. The method of  claim 16 , further comprising:
 applying bias to influence positioning of connectors on additional wires in a full circuit so as to reduce variance in a number of connectors.  
 
     
     
       18. A method, comprising:
 placing, in a nanoscale circuit, a first connector between a first addressing wire and a first nanowire;  
 applying a bias to the nanoscale circuit; and  
 placing, while applying the bias to the nanoscale circuit, a second connector between a second addressing wire and a second nanowire to influence a placement location of the second connector on the nanoscale circuit.  
 
     
     
       19. The method of  claim 18  wherein placing while applying the bias to the nanoscale circuit further comprises introducing a voltage on at least the first addressing wire to influence the placement location of the second connector on the nanoscale circuit. 
     
     
       20. The method of  claim 18  wherein placing while applying the bias to the nanoscale circuit further comprises introducing a charge on the first and second nanowires to influence the placement location of the second connector on the nanoscale circuit.