Design-for-test modes for a phase locked loop

Abstract

There is a desire to provide a testing method and apparatus that can be successfully integrated into a PLL and PLL-like circuits (e.g. frequency synthesizers, delay lock loops, etc.). It is desirable that the PLL or PLL-like circuit integrated with testing apparatus does not suffer from performance degradations during nominal (mission mode) operation. Furthermore, it is desirable that the PLL and the testing apparatus share the same interface. In order to produce a PLL having integrated testing apparatus, without having the PLL suffer severe performance degradations during nominal operation nor having the combination of the PLL and testing apparatus be unnecessarily large, a modified PLL integrated with testing apparatus is provided.

1. A Phase-Locked Loop (PLL) integrated with testing apparatus comprising in a loop:
 i) a Phase-Frequency Detector (PFD), the PFD having first and second signal inputs, a test control input and an output, wherein the test control input is used to switch the PFD between a normal operating mode, in which the output delivers an output signal containing the phase and frequency difference between first and second signals applied respectively to the first and second signal inputs, and a transparent mode, in which only one of the first and second signal inputs is coupled to the output such that the corresponding signal is coupled through to the output unaltered;  
 ii) a Voltage Controlled Oscillator (VCO), the VCO having an input and an output, the input of the VCO connected to the output of the PFD;  
 iii) a frequency divider, the frequency divider having an input and an output, the input of the frequency divider connected to the output of the VCO; and  
 iv) a first multiplexer (MUX), the first MUX having first and second signal inputs, a control input and an output, the output of the first MUX connected to the second signal input of the PFD, the first signal input of the first MUX connected to the output of the frequency divider, the second signal input coupled to receive a bias signal, and the control input coupled to receive a control signal;  
 wherein the control signal coupled to the control input of the first MUX is set to select which one of the first and second signal inputs is coupled to the output of the first MUX.  
 
   
   
     2. The PLL of  claim 1  further comprising a charge pump, the charge pump having an input and an output, the charge pump connected between the PFD and the VCO. 
   
   
     3. The PLL of  claim 1  further comprising a loop filter connected to the input of the VCO. 
   
   
     4. The PLL of  claim 1  further comprising a loop filter connected between the PFD and the VCO. 
   
   
     5. The PLL of  claim 1  further comprising a third MUX having first and second signal inputs, a control input and an output, the output of the third MUX connected to the first input of the PFD, the first signal input of the third MUX coupled to receive a reference signal, the second signal input of the third MUX coupled to receive a second bias signal, and the control input of the third MUX coupled to receive a third control signal, wherein the third control signal coupled to the control input of the third MUX is set to select which one of the first and second signal inputs is coupled to the output of the third MUX. 
   
   
     6. The PLL of  claim 5  further comprising a reference divider circuit, the reference divider having an input and an output, the input coupled to receive the reference signal and the output connected to the first signal input of the third MUX to provide a signal to the third MUX derived from the reference signal. 
   
   
     7. The PLL of  claim 1  further comprising a second MUX between VCO and the frequency divider, the second MUX having first and second signal inputs, a control input and an output, the output of the second MUX connected to the input of the frequency divider, the first, signal input of the second MUX connected to the output of the VCO, the second signal input of the second MUX coupled to receive a first test signal, and the control input of the second MUX coupled to receive a second control signal, wherein the second control signal coupled to the control input of the second MUX is set to select which one of the first and second signal inputs is coupled to the output of the second MUX. 
   
   
     8. The PLL of  claim 7  further comprising a mixer connected between the VCO and the second MUX, the mixer having two inputs and an output, the output of the mixer connected to the first signal input of the second MUX, the first input of the mixer coupled to receive the output of the VCO and the second input of the mixer coupled to receive a local reference signal. 
   
   
     9. The PLL of  claim 8  further comprising a local oscillator, the local oscillator providing the local reference signal. 
   
   
     10. The PLL of  claim 9  further comprising a fourth MUX between the local oscillator and the second input of the mixer, the fourth MUX having first and second signal input, a control input and an output, the first signal input of the fourth MUX coupled to receive the local reference signal, the second signal input of the fourth MUX coupled to receive a fourth bias signal, the output of the fourth MUX connected to the second input of the mixer, and the control input of the fourth MUX coupled to receive a fourth control signal, the fourth control signal set to select which of the two signal inputs is coupled to the output of the fourth MUX. 
   
   
     11. A Phase-Locked Loop (PLL) integrated with testing apparatus comprising in a loop:
 i) a Phase-Frequency Detector (PFD), the PFD having first and second signal inputs, a test control input and an output, wherein the test control input is used to switch the PFD between a normal operating mode, in which the output delivers an output signal containing the phase and frequency difference between first and second signals applied respectively to the first and second signal inputs, and a transparent node, in which only one of the first and second signal inputs is coupled to the output such that the corresponding signal is coupled through to the output unaltered;  
 ii) a Voltage Controlled Oscillator (VCO), the VCO having an input and an output, the input of the VCO connected to the output of the PFD;  
 iii) a frequency divider, the frequency divider having an input and an output, the output of the frequency divider connected to the; second signal input of the PFD; and  
 iv) a first multiplexer (MUX), the first MUX having first and second signal inputs, a control input and an output, the output of the first MUX connected to the input of the frequency divider, the first signal input of the first MUX is connected to the output of the VCO, the second signal input of the first MUX coupled to receive a first test signal, and the control input of the first MUX coupled to receive a first control signal, wherein the first control signal coupled to the control input of the first MUX is set to select which one of the first and second signal inputs is coupled to the output of the first MUX.  
 
   
   
     12. The PLL of  claim 11  further comprising a charge pump, the charge pump having an input and an output, the charge connected between the PFD and the VCO. 
   
   
     13. The PIL of  claim 11  further comprising a loop filter connected to the input of the VCO. 
   
   
     14. The PLL of  claim 11  further comprising a loop filter connected between the PFD and the VCO. 
   
   
     15. The PLL of  claim 11  further comprising a third MUX having first and second signal inputs, a control input and an output, the output of the third MUX connected to the first input of the PFD, the first signal input of the third MUX is coupled to receive a reference signal, the second signal input of the third MUX coupled to receive a second bias signal, and the control input of the third MUX coupled to receive a third control signal, wherein the third control signal coupled to the control input of the third MUX is set to select which one of the first and second signal inputs is coupled to the output of the third MUX. 
   
   
     16. The PLL of  claim 15  further comprising a reference divider circuit, the reference divider having an input and an output, the input coupled to receive the reference signal and the output connected to the first signal input of the third MUX to provide a signal to the third MUX derived from the reference signal.